DE69424388T2 - Verfahren und Dielektrikumstruktur zur Erleichterung der Metallüberätzung ohne Beschädigung des Zwischendielektrikums - Google Patents

Verfahren und Dielektrikumstruktur zur Erleichterung der Metallüberätzung ohne Beschädigung des Zwischendielektrikums

Info

Publication number
DE69424388T2
DE69424388T2 DE69424388T DE69424388T DE69424388T2 DE 69424388 T2 DE69424388 T2 DE 69424388T2 DE 69424388 T DE69424388 T DE 69424388T DE 69424388 T DE69424388 T DE 69424388T DE 69424388 T2 DE69424388 T2 DE 69424388T2
Authority
DE
Germany
Prior art keywords
dielectric
overetching
damaging
facilitate metal
dielectric structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69424388T
Other languages
English (en)
Other versions
DE69424388D1 (de
Inventor
John C Sardella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69424388D1 publication Critical patent/DE69424388D1/de
Application granted granted Critical
Publication of DE69424388T2 publication Critical patent/DE69424388T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69424388T 1993-12-23 1994-11-25 Verfahren und Dielektrikumstruktur zur Erleichterung der Metallüberätzung ohne Beschädigung des Zwischendielektrikums Expired - Fee Related DE69424388T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17249193A 1993-12-23 1993-12-23

Publications (2)

Publication Number Publication Date
DE69424388D1 DE69424388D1 (de) 2000-06-15
DE69424388T2 true DE69424388T2 (de) 2000-08-31

Family

ID=22627918

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69424388T Expired - Fee Related DE69424388T2 (de) 1993-12-23 1994-11-25 Verfahren und Dielektrikumstruktur zur Erleichterung der Metallüberätzung ohne Beschädigung des Zwischendielektrikums

Country Status (3)

Country Link
US (1) US5766974A (de)
EP (1) EP0660393B1 (de)
DE (1) DE69424388T2 (de)

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US5763910A (en) * 1995-01-31 1998-06-09 Fujitsu Limited Semiconductor device having a through-hole formed on diffused layer by self-alignment
US5883007A (en) * 1996-12-20 1999-03-16 Lam Research Corporation Methods and apparatuses for improving photoresist selectivity and reducing etch rate loading
US6060385A (en) * 1997-02-14 2000-05-09 Micro Technology, Inc. Method of making an interconnect structure
KR100266749B1 (ko) * 1997-06-11 2000-09-15 윤종용 반도체 장치의 콘택 플러그 형성 방법
US6025263A (en) * 1997-07-15 2000-02-15 Nanya Technology Corporation Underlayer process for high O3 /TEOS interlayer dielectric deposition
US6103593A (en) * 1998-02-13 2000-08-15 Advanced Micro Devices, Inc. Method and system for providing a contact on a semiconductor device
US6228760B1 (en) 1999-03-08 2001-05-08 Taiwan Semiconductor Manufacturing Company Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish
US6242362B1 (en) 1999-08-04 2001-06-05 Taiwan Semiconductor Manufacturing Company Etch process for fabricating a vertical hard mask/conductive pattern profile to improve T-shaped profile for a silicon oxynitride hard mask
US6297162B1 (en) 1999-09-27 2001-10-02 Taiwan Semiconductor Manufacturing Company Method to reduce silicon oxynitride etch rate in a silicon oxide dry etch
US6274499B1 (en) 1999-11-19 2001-08-14 Chartered Semiconductor Manufacturing Ltd. Method to avoid copper contamination during copper etching and CMP
US6207566B1 (en) * 1999-12-02 2001-03-27 United Microelectronics Corp. Method for forming a metal plug on a semiconductor wafer
DE10057463A1 (de) * 2000-11-20 2002-05-29 Promos Technologies Inc Herstellungsverfahren für eine Metallleitung
EP1595282A1 (de) 2003-02-07 2005-11-16 Koninklijke Philips Electronics N.V. METALLûTZVERFAHREN FÜR EINE VERBINDUNGSSTRUKTUR UND DURCH EINSOLCHES VERFAHREN ERHALTENE METALLVERBINDUNGSSTRUKTUR
US8463080B1 (en) 2004-01-22 2013-06-11 Vescent Photonics, Inc. Liquid crystal waveguide having two or more control voltages for controlling polarized light
US20050271325A1 (en) * 2004-01-22 2005-12-08 Anderson Michael H Liquid crystal waveguide having refractive shapes for dynamically controlling light
US8989523B2 (en) 2004-01-22 2015-03-24 Vescent Photonics, Inc. Liquid crystal waveguide for dynamically controlling polarized light
US8860897B1 (en) 2004-01-22 2014-10-14 Vescent Photonics, Inc. Liquid crystal waveguide having electric field orientated for controlling light
US7720116B2 (en) * 2004-01-22 2010-05-18 Vescent Photonics, Inc. Tunable laser having liquid crystal waveguide
US7570320B1 (en) 2005-09-01 2009-08-04 Vescent Photonics, Inc. Thermo-optic liquid crystal waveguides
US9366938B1 (en) 2009-02-17 2016-06-14 Vescent Photonics, Inc. Electro-optic beam deflector device
US8995038B1 (en) 2010-07-06 2015-03-31 Vescent Photonics, Inc. Optical time delay control device
JP6536814B2 (ja) * 2015-09-18 2019-07-03 サンケン電気株式会社 半導体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2024505B (en) * 1978-05-26 1983-03-23 Rockwell International Corp Manufacture of integrated circuits
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4412885A (en) * 1982-11-03 1983-11-01 Applied Materials, Inc. Materials and methods for plasma etching of aluminum and aluminum alloys
US4444618A (en) * 1983-03-03 1984-04-24 General Electric Company Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys
US4505782A (en) * 1983-03-25 1985-03-19 Lfe Corporation Plasma reactive ion etching of aluminum and aluminum alloys
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
JP2556138B2 (ja) * 1989-06-30 1996-11-20 日本電気株式会社 半導体装置の製造方法
JPH03156927A (ja) * 1989-10-24 1991-07-04 Hewlett Packard Co <Hp> アルミ・メタライゼーションのパターン形成方法
JP3170791B2 (ja) * 1990-09-11 2001-05-28 ソニー株式会社 Ａｌ系材料膜のエッチング方法
JPH04355916A (ja) * 1990-10-12 1992-12-09 Seiko Epson Corp ドライエッチング装置
US5117273A (en) * 1990-11-16 1992-05-26 Sgs-Thomson Microelectronics, Inc. Contact for integrated circuits
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
US5318667A (en) * 1991-04-04 1994-06-07 Hitachi, Ltd. Method and apparatus for dry etching
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5288665A (en) * 1992-08-12 1994-02-22 Applied Materials, Inc. Process for forming low resistance aluminum plug in via electrically connected to overlying patterned metal layer for integrated circuit structures
JPH06151382A (ja) * 1992-11-11 1994-05-31 Toshiba Corp ドライエッチング方法
US5444022A (en) * 1993-12-29 1995-08-22 Intel Corporation Method of fabricating an interconnection structure for an integrated circuit
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same

Also Published As

Publication number Publication date
EP0660393A1 (de) 1995-06-28
US5766974A (en) 1998-06-16
DE69424388D1 (de) 2000-06-15
EP0660393B1 (de) 2000-05-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee