DE2239686A1 - Verfahren zur herstellung von dielektrisch isolierten schichtbereichen aus einem siliciumhalbleitermaterial auf einer traegerschicht - Google Patents

Verfahren zur herstellung von dielektrisch isolierten schichtbereichen aus einem siliciumhalbleitermaterial auf einer traegerschicht

Info

Publication number
DE2239686A1
DE2239686A1 DE2239686A DE2239686A DE2239686A1 DE 2239686 A1 DE2239686 A1 DE 2239686A1 DE 2239686 A DE2239686 A DE 2239686A DE 2239686 A DE2239686 A DE 2239686A DE 2239686 A1 DE2239686 A1 DE 2239686A1
Authority
DE
Germany
Prior art keywords
layer
silicon
boron
doped
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2239686A
Other languages
German (de)
English (en)
Inventor
Robert Guy Hays
Chongkook Rhee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE2239686A1 publication Critical patent/DE2239686A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019—Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Element Separation (AREA)
  • Weting (AREA)
DE2239686A 1971-08-13 1972-08-11 Verfahren zur herstellung von dielektrisch isolierten schichtbereichen aus einem siliciumhalbleitermaterial auf einer traegerschicht Pending DE2239686A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17145371A 1971-08-13 1971-08-13

Publications (1)

Publication Number Publication Date
DE2239686A1 true DE2239686A1 (de) 1973-03-08

Family

ID=22623784

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2239686A Pending DE2239686A1 (de) 1971-08-13 1972-08-11 Verfahren zur herstellung von dielektrisch isolierten schichtbereichen aus einem siliciumhalbleitermaterial auf einer traegerschicht

Country Status (3)

Country Link
US (1) US3721588A (enExample)
JP (1) JPS4828181A (enExample)
DE (1) DE2239686A1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929528A (en) * 1973-01-12 1975-12-30 Motorola Inc Fabrication of monocriptalline silicon on insulating substrates utilizing selective etching and deposition techniques
US3892606A (en) * 1973-06-28 1975-07-01 Ibm Method for forming silicon conductive layers utilizing differential etching rates
US3855009A (en) * 1973-09-20 1974-12-17 Texas Instruments Inc Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers
US4050979A (en) * 1973-12-28 1977-09-27 Texas Instruments Incorporated Process for thinning silicon with special application to producing silicon on insulator
JPS50127255A (enExample) * 1974-03-25 1975-10-07
JPS5329551B2 (enExample) * 1974-08-19 1978-08-22
US4137123A (en) * 1975-12-31 1979-01-30 Motorola, Inc. Texture etching of silicon: method
US4372803A (en) * 1980-09-26 1983-02-08 The United States Of America As Represented By The Secretary Of The Navy Method for etch thinning silicon devices
US4408386A (en) * 1980-12-12 1983-10-11 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor integrated circuit devices
US4554059A (en) * 1983-11-04 1985-11-19 Harris Corporation Electrochemical dielectric isolation technique
US5343064A (en) * 1988-03-18 1994-08-30 Spangler Leland J Fully integrated single-crystal silicon-on-insulator process, sensors and circuits
US5136344A (en) * 1988-11-02 1992-08-04 Universal Energy Systems, Inc. High energy ion implanted silicon on insulator structure
EP0413042B1 (en) * 1989-08-16 1992-12-16 International Business Machines Corporation Method of producing micromechanical sensors for the afm/stm profilometry and micromechanical afm/stm sensor head
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5159429A (en) * 1990-01-23 1992-10-27 International Business Machines Corporation Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same
US5145795A (en) * 1990-06-25 1992-09-08 Motorola, Inc. Semiconductor device and method therefore
US5064498A (en) * 1990-08-21 1991-11-12 Texas Instruments Incorporated Silicon backside etch for semiconductors
US5213986A (en) * 1992-04-10 1993-05-25 North American Philips Corporation Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning
US11295949B2 (en) * 2019-04-01 2022-04-05 Vishay SIliconix, LLC Virtual wafer techniques for fabricating semiconductor devices

Also Published As

Publication number Publication date
US3721588A (en) 1973-03-20
JPS4828181A (enExample) 1973-04-13

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