DE2106069A1 - Verfahren und Anordnung zur Addition - Google Patents

Verfahren und Anordnung zur Addition

Info

Publication number
DE2106069A1
DE2106069A1 DE19712106069 DE2106069A DE2106069A1 DE 2106069 A1 DE2106069 A1 DE 2106069A1 DE 19712106069 DE19712106069 DE 19712106069 DE 2106069 A DE2106069 A DE 2106069A DE 2106069 A1 DE2106069 A1 DE 2106069A1
Authority
DE
Germany
Prior art keywords
decimal
carry
bit
functions
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712106069
Other languages
German (de)
English (en)
Inventor
Martin Stanley Pough keepsie Weinberger Arnold Newburgh NY Schmookler (V St A )
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2106069A1 publication Critical patent/DE2106069A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
DE19712106069 1970-02-13 1971-02-09 Verfahren und Anordnung zur Addition Pending DE2106069A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1124670A 1970-02-13 1970-02-13

Publications (1)

Publication Number Publication Date
DE2106069A1 true DE2106069A1 (de) 1971-08-19

Family

ID=21749503

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712106069 Pending DE2106069A1 (de) 1970-02-13 1971-02-09 Verfahren und Anordnung zur Addition

Country Status (5)

Country Link
US (1) US3629565A (enExample)
JP (1) JPS531615B1 (enExample)
DE (1) DE2106069A1 (enExample)
FR (1) FR2080412A5 (enExample)
GB (1) GB1270909A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2352686B2 (de) * 1973-10-20 1978-05-11 Vereinigte Flugtechnische Werke- Fokker Gmbh, 2800 Bremen Dezimaler Parallel-Addierer/Substrahierer
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
US4118786A (en) * 1977-01-10 1978-10-03 International Business Machines Corporation Integrated binary-BCD look-ahead adder
US4644489A (en) * 1984-02-10 1987-02-17 Prime Computer, Inc. Multi-format binary coded decimal processor with selective output formatting
US4805131A (en) * 1987-07-09 1989-02-14 Digital Equipment Corporation BCD adder circuit
US7299254B2 (en) * 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US7519647B2 (en) * 2005-02-09 2009-04-14 International Business Machines Corporation System and method for providing a decimal multiply algorithm using a double adder
US7475104B2 (en) * 2005-02-09 2009-01-06 International Business Machines Corporation System and method for providing a double adder for decimal floating point operations
US7519645B2 (en) * 2005-02-10 2009-04-14 International Business Machines Corporation System and method for performing decimal floating point addition

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3308284A (en) * 1963-06-28 1967-03-07 Ibm Qui-binary adder and readout latch
GB1103384A (en) * 1964-03-02 1968-02-14 Olivetti & Co Spa Improvements in or relating to electronic computers

Also Published As

Publication number Publication date
FR2080412A5 (enExample) 1971-11-12
GB1270909A (en) 1972-04-19
JPS531615B1 (enExample) 1978-01-20
US3629565A (en) 1971-12-21

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