DE68927488T2 - Binäre Übertragvorgriffsschaltung - Google Patents

Binäre Übertragvorgriffsschaltung

Info

Publication number
DE68927488T2
DE68927488T2 DE68927488T DE68927488T DE68927488T2 DE 68927488 T2 DE68927488 T2 DE 68927488T2 DE 68927488 T DE68927488 T DE 68927488T DE 68927488 T DE68927488 T DE 68927488T DE 68927488 T2 DE68927488 T2 DE 68927488T2
Authority
DE
Germany
Prior art keywords
forward circuit
carry forward
binary carry
binary
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927488T
Other languages
English (en)
Other versions
DE68927488D1 (de
Inventor
Gensuke Goto
Hajime Kubosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63097754A external-priority patent/JP2563467B2/ja
Priority claimed from JP63110889A external-priority patent/JP2563473B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68927488D1 publication Critical patent/DE68927488D1/de
Publication of DE68927488T2 publication Critical patent/DE68927488T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4812—Multiplexers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
DE68927488T 1988-04-20 1989-04-19 Binäre Übertragvorgriffsschaltung Expired - Fee Related DE68927488T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63097754A JP2563467B2 (ja) 1988-04-20 1988-04-20 ２進演算器
JP63110889A JP2563473B2 (ja) 1988-05-07 1988-05-07 ２進演算器

Publications (2)

Publication Number Publication Date
DE68927488D1 DE68927488D1 (de) 1997-01-09
DE68927488T2 true DE68927488T2 (de) 1997-03-20

Family

ID=26438905

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927488T Expired - Fee Related DE68927488T2 (de) 1988-04-20 1989-04-19 Binäre Übertragvorgriffsschaltung

Country Status (4)

Country Link
US (1) US5434810A (de)
EP (1) EP0347029B1 (de)
KR (1) KR920003517B1 (de)
DE (1) DE68927488T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0564137B1 (de) * 1992-03-31 2001-06-20 STMicroelectronics, Inc. Parallelisierter Übertragvorgriffsaddierer
US5400007A (en) * 1992-04-30 1995-03-21 Sgs-Thomson Microelectronics, Inc. Multiple level parallel magnitude comparator
US5619443A (en) * 1995-03-31 1997-04-08 International Business Machines Corporation Carry select and input select adder for late arriving data
JPH09148916A (ja) * 1995-11-24 1997-06-06 Nec Corp 半導体集積回路
US5732008A (en) * 1995-12-04 1998-03-24 The University Of Waterloo Low-power high performance adder
US5943251A (en) * 1996-11-18 1999-08-24 Samsung Electronics Co., Ltd. Adder which handles multiple data with different data types
KR100244396B1 (ko) * 1996-12-30 2000-02-01 김영환 캐리 룩어헤드 가산기
KR100475012B1 (ko) * 1997-10-08 2005-04-14 삼성전자주식회사 그룹데이터에대한산술연산을수행하는64비트산술연산기
US5964827A (en) * 1997-11-17 1999-10-12 International Business Machines Corporation High-speed binary adder
US6539413B1 (en) * 2000-03-15 2003-03-25 Agere Systems Inc. Prefix tree adder with efficient sum generation
US6990508B1 (en) * 2001-09-11 2006-01-24 Cypress Semiconductor Corp. High performance carry chain with reduced macrocell logic and fast carry lookahead
US7739324B1 (en) 2006-03-22 2010-06-15 Cadence Design Systems, Inc. Timing driven synthesis of sum-of-product functional blocks

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3553446A (en) * 1966-08-04 1971-01-05 Honeywell Inc Carry determination logic
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
US4525797A (en) * 1983-01-03 1985-06-25 Motorola, Inc. N-bit carry select adder circuit having only one full adder per bit
US4559609A (en) * 1983-02-07 1985-12-17 At&T Bell Laboratories Full adder using transmission gates
DE3346241A1 (de) * 1983-03-31 1984-10-04 Siemens AG, 1000 Berlin und 8000 München Parallelverknuepfungsschaltung mit verkuerztem uebertragsdurchlauf
JPS60105041A (ja) * 1983-11-14 1985-06-10 Nec Corp 加算器
JPS6149233A (ja) * 1984-08-17 1986-03-11 Nec Corp 高速デジタル加減算回路
JPS61226836A (ja) * 1985-03-30 1986-10-08 Toshiba Corp 桁上げ選択加算器

Also Published As

Publication number Publication date
KR920003517B1 (en) 1992-05-02
EP0347029A3 (de) 1991-08-07
EP0347029B1 (de) 1996-11-27
DE68927488D1 (de) 1997-01-09
US5434810A (en) 1995-07-18
KR900016859A (ko) 1990-11-14
EP0347029A2 (de) 1989-12-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee