JPS531615B1 - - Google Patents

Info

Publication number
JPS531615B1
JPS531615B1 JP566271A JP566271A JPS531615B1 JP S531615 B1 JPS531615 B1 JP S531615B1 JP 566271 A JP566271 A JP 566271A JP 566271 A JP566271 A JP 566271A JP S531615 B1 JPS531615 B1 JP S531615B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP566271A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS531615B1 publication Critical patent/JPS531615B1/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting
JP566271A 1970-02-13 1971-02-12 Pending JPS531615B1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1124670A 1970-02-13 1970-02-13

Publications (1)

Publication Number Publication Date
JPS531615B1 true JPS531615B1 (ja) 1978-01-20

Family

ID=21749503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP566271A Pending JPS531615B1 (ja) 1970-02-13 1971-02-12

Country Status (5)

Country Link
US (1) US3629565A (ja)
JP (1) JPS531615B1 (ja)
DE (1) DE2106069A1 (ja)
FR (1) FR2080412A5 (ja)
GB (1) GB1270909A (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2352686B2 (de) * 1973-10-20 1978-05-11 Vereinigte Flugtechnische Werke- Fokker Gmbh, 2800 Bremen Dezimaler Parallel-Addierer/Substrahierer
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
US4118786A (en) * 1977-01-10 1978-10-03 International Business Machines Corporation Integrated binary-BCD look-ahead adder
US4644489A (en) * 1984-02-10 1987-02-17 Prime Computer, Inc. Multi-format binary coded decimal processor with selective output formatting
US4805131A (en) * 1987-07-09 1989-02-14 Digital Equipment Corporation BCD adder circuit
US7299254B2 (en) * 2003-11-24 2007-11-20 International Business Machines Corporation Binary coded decimal addition
US7475104B2 (en) 2005-02-09 2009-01-06 International Business Machines Corporation System and method for providing a double adder for decimal floating point operations
US7519647B2 (en) 2005-02-09 2009-04-14 International Business Machines Corporation System and method for providing a decimal multiply algorithm using a double adder
US7519645B2 (en) * 2005-02-10 2009-04-14 International Business Machines Corporation System and method for performing decimal floating point addition

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3308284A (en) * 1963-06-28 1967-03-07 Ibm Qui-binary adder and readout latch
GB1103384A (en) * 1964-03-02 1968-02-14 Olivetti & Co Spa Improvements in or relating to electronic computers

Also Published As

Publication number Publication date
DE2106069A1 (de) 1971-08-19
GB1270909A (en) 1972-04-19
FR2080412A5 (ja) 1971-11-12
US3629565A (en) 1971-12-21

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