DE2101609C3 - Kontaktanordnung für ein Halbleiterbauelement - Google Patents

Kontaktanordnung für ein Halbleiterbauelement

Info

Publication number
DE2101609C3
DE2101609C3 DE2101609A DE2101609A DE2101609C3 DE 2101609 C3 DE2101609 C3 DE 2101609C3 DE 2101609 A DE2101609 A DE 2101609A DE 2101609 A DE2101609 A DE 2101609A DE 2101609 C3 DE2101609 C3 DE 2101609C3
Authority
DE
Germany
Prior art keywords
heat
silicon
resistant
layer
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2101609A
Other languages
German (de)
English (en)
Other versions
DE2101609A1 (de
DE2101609B2 (de
Inventor
Frederic Leroy Oldwick N.J. Katnack (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE2101609A1 publication Critical patent/DE2101609A1/de
Publication of DE2101609B2 publication Critical patent/DE2101609B2/de
Application granted granted Critical
Publication of DE2101609C3 publication Critical patent/DE2101609C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
DE2101609A 1970-10-29 1971-01-14 Kontaktanordnung für ein Halbleiterbauelement Expired DE2101609C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8495870A 1970-10-29 1970-10-29

Publications (3)

Publication Number Publication Date
DE2101609A1 DE2101609A1 (de) 1972-05-04
DE2101609B2 DE2101609B2 (de) 1973-06-20
DE2101609C3 true DE2101609C3 (de) 1974-01-10

Family

ID=22188279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2101609A Expired DE2101609C3 (de) 1970-10-29 1971-01-14 Kontaktanordnung für ein Halbleiterbauelement

Country Status (6)

Country Link
US (1) US3667008A (https=)
JP (1) JPS5038553B1 (https=)
BE (1) BE761668A (https=)
DE (1) DE2101609C3 (https=)
GB (1) GB1296951A (https=)
YU (1) YU36420B (https=)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909319A (en) * 1971-02-23 1975-09-30 Shohei Fujiwara Planar structure semiconductor device and method of making the same
DE2251727A1 (de) * 1972-10-21 1974-04-25 Licentia Gmbh Halbleiteranordnung mit mindestens zwei zonen entgegengesetzten leitfaehigkeitstyps
GB1399163A (en) * 1972-11-08 1975-06-25 Ferranti Ltd Methods of manufacturing semiconductor devices
US4106051A (en) * 1972-11-08 1978-08-08 Ferranti Limited Semiconductor devices
US3886578A (en) * 1973-02-26 1975-05-27 Multi State Devices Ltd Low ohmic resistance platinum contacts for vanadium oxide thin film devices
US3860945A (en) * 1973-03-29 1975-01-14 Rca Corp High frequency voltage-variable capacitor
US4042953A (en) * 1973-08-01 1977-08-16 Micro Power Systems, Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4096510A (en) * 1974-08-19 1978-06-20 Matsushita Electric Industrial Co., Ltd. Thermal printing head
US3988759A (en) * 1974-08-26 1976-10-26 Rca Corporation Thermally balanced PN junction
US4152823A (en) * 1975-06-10 1979-05-08 Micro Power Systems High temperature refractory metal contact assembly and multiple layer interconnect structure
US4127863A (en) * 1975-10-01 1978-11-28 Tokyo Shibaura Electric Co., Ltd. Gate turn-off type thyristor with separate semiconductor resistive wafer providing emitter ballast
JPS5917852B2 (ja) * 1977-02-07 1984-04-24 日本電気株式会社 半導体装置
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4234889A (en) * 1977-05-31 1980-11-18 Texas Instruments Incorporated Metal-to-moat contacts in N-channel silicon gate integrated circuits using discrete second-level polycrystalline silicon
US4240097A (en) * 1977-05-31 1980-12-16 Texas Instruments Incorporated Field-effect transistor structure in multilevel polycrystalline silicon
US4209716A (en) * 1977-05-31 1980-06-24 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in second-level polycrystalline silicon layer
NL190710C (nl) * 1978-02-10 1994-07-01 Nec Corp Geintegreerde halfgeleiderketen.
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
JPS55138273A (en) * 1979-04-11 1980-10-28 Fujitsu Ltd Transistor
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4291322A (en) * 1979-07-30 1981-09-22 Bell Telephone Laboratories, Incorporated Structure for shallow junction MOS circuits
EP0030147B1 (en) * 1979-11-29 1983-05-11 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor integrated circuit
DE3135007A1 (de) * 1981-09-04 1983-03-24 Licentia Gmbh Mehrschichtenkontakt fuer eine halbleiteranordnung
JPS5921034A (ja) * 1982-07-27 1984-02-02 Toshiba Corp 半導体装置
US4888297A (en) * 1982-09-20 1989-12-19 International Business Machines Corporation Process for making a contact structure including polysilicon and metal alloys
DE3688711T2 (de) * 1985-03-07 1993-12-16 Toshiba Kawasaki Kk Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung.
US5280188A (en) * 1985-03-07 1994-01-18 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors
US4794093A (en) * 1987-05-01 1988-12-27 Raytheon Company Selective backside plating of gaas monolithic microwave integrated circuits
US4949162A (en) * 1987-06-05 1990-08-14 Hitachi, Ltd. Semiconductor integrated circuit with dummy pedestals
FR2618254B1 (fr) * 1987-07-16 1990-01-05 Thomson Semiconducteurs Procede et structure de prise de contact sur des plots de circuit integre.
JP2894777B2 (ja) * 1990-03-02 1999-05-24 日本電気株式会社 半導体装置
US5355015A (en) * 1990-12-13 1994-10-11 National Semiconductor Corporation High breakdown lateral PNP transistor
US5567988A (en) * 1993-08-13 1996-10-22 Lsi Logic Corporation Integrated circuit interconnect structure with back reflection suppressing electronic "speed bumps"
DE69321965T2 (de) * 1993-12-24 1999-06-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania MOS-Leistungs-Chip-Typ und Packungszusammenbau
EP0660402B1 (en) * 1993-12-24 1998-11-04 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Power semiconductor device
US5798287A (en) * 1993-12-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Method for forming a power MOS device chip
US5767546A (en) * 1994-12-30 1998-06-16 Siliconix Incorporated Laternal power mosfet having metal strap layer to reduce distributed resistance

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3504239A (en) * 1964-01-31 1970-03-31 Rca Corp Transistor with distributed resistor between emitter lead and emitter region
US3443175A (en) * 1967-03-22 1969-05-06 Rca Corp Pn-junction semiconductor with polycrystalline layer on one region
US3460007A (en) * 1967-07-03 1969-08-05 Rca Corp Semiconductor junction device
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation
US3559003A (en) * 1969-01-03 1971-01-26 Ibm Universal metallurgy for semiconductor materials

Also Published As

Publication number Publication date
DE2101609A1 (de) 1972-05-04
JPS5038553B1 (https=) 1975-12-10
YU20671A (en) 1981-11-13
GB1296951A (https=) 1972-11-22
US3667008A (en) 1972-05-30
BE761668A (fr) 1971-06-16
DE2101609B2 (de) 1973-06-20
YU36420B (en) 1983-06-30

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)