DE2021809A1 - Elektrische Verbindungsanordnung zwischen Mehrlagen-Metallisierungsebenen auf einem Halbleiterkristall - Google Patents

Elektrische Verbindungsanordnung zwischen Mehrlagen-Metallisierungsebenen auf einem Halbleiterkristall

Info

Publication number
DE2021809A1
DE2021809A1 DE19702021809 DE2021809A DE2021809A1 DE 2021809 A1 DE2021809 A1 DE 2021809A1 DE 19702021809 DE19702021809 DE 19702021809 DE 2021809 A DE2021809 A DE 2021809A DE 2021809 A1 DE2021809 A1 DE 2021809A1
Authority
DE
Germany
Prior art keywords
metallization
semiconductor crystal
layer
diffusion region
metallization levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19702021809
Other languages
German (de)
English (en)
Other versions
DE2021809B2 (enExample
Inventor
Ruoff Carl Edward
Curtis John Joseph
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2021809A1 publication Critical patent/DE2021809A1/de
Publication of DE2021809B2 publication Critical patent/DE2021809B2/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
DE19702021809 1969-05-05 1970-05-04 Elektrische Verbindungsanordnung zwischen Mehrlagen-Metallisierungsebenen auf einem Halbleiterkristall Ceased DE2021809A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82159269A 1969-05-05 1969-05-05

Publications (2)

Publication Number Publication Date
DE2021809A1 true DE2021809A1 (de) 1970-11-19
DE2021809B2 DE2021809B2 (enExample) 1980-02-28

Family

ID=25233779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702021809 Ceased DE2021809A1 (de) 1969-05-05 1970-05-04 Elektrische Verbindungsanordnung zwischen Mehrlagen-Metallisierungsebenen auf einem Halbleiterkristall

Country Status (5)

Country Link
US (1) US3577036A (enExample)
JP (1) JPS4813877B1 (enExample)
DE (1) DE2021809A1 (enExample)
FR (1) FR2046204A5 (enExample)
GB (1) GB1252097A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3774079A (en) * 1971-06-25 1973-11-20 Ibm Monolithically fabricated tranistor circuit with multilayer conductive patterns
US4109275A (en) * 1976-12-22 1978-08-22 International Business Machines Corporation Interconnection of integrated circuit metallization
JPH08130246A (ja) * 1994-10-28 1996-05-21 Ricoh Co Ltd 半導体装置とその製造方法
DE19824400C2 (de) * 1998-05-30 2000-05-18 Bosch Gmbh Robert Leiterbahn-Kontaktierungsanordnung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303071A (en) * 1964-10-27 1967-02-07 Bell Telephone Labor Inc Fabrication of a semiconductive device with closely spaced electrodes
US3419765A (en) * 1965-10-01 1968-12-31 Texas Instruments Inc Ohmic contact to semiconductor devices

Also Published As

Publication number Publication date
US3577036A (en) 1971-05-04
JPS4813877B1 (enExample) 1973-05-01
FR2046204A5 (enExample) 1971-03-05
GB1252097A (enExample) 1971-11-03
DE2021809B2 (enExample) 1980-02-28

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Legal Events

Date Code Title Description
8235 Patent refused