DE19781675T1 - Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen - Google Patents

Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen

Info

Publication number
DE19781675T1
DE19781675T1 DE19781675T DE19781675T DE19781675T1 DE 19781675 T1 DE19781675 T1 DE 19781675T1 DE 19781675 T DE19781675 T DE 19781675T DE 19781675 T DE19781675 T DE 19781675T DE 19781675 T1 DE19781675 T1 DE 19781675T1
Authority
DE
Germany
Prior art keywords
crossovers
memory cell
vertically stacked
cell design
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19781675T
Other languages
German (de)
English (en)
Other versions
DE19781675B4 (de
Inventor
Mark T Bohr
Jeffrey K Greason
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19781675T1 publication Critical patent/DE19781675T1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
DE19781675T 1996-03-28 1997-03-20 Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen Pending DE19781675T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62346396A 1996-03-28 1996-03-28
PCT/US1997/004686 WO1997036330A1 (en) 1996-03-28 1997-03-20 Memory cell design with vertically stacked crossovers

Publications (1)

Publication Number Publication Date
DE19781675T1 true DE19781675T1 (de) 1999-03-18

Family

ID=24498170

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19781675T Pending DE19781675T1 (de) 1996-03-28 1997-03-20 Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen
DE19781675A Expired - Fee Related DE19781675B4 (de) 1996-03-28 1997-03-20 Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19781675A Expired - Fee Related DE19781675B4 (de) 1996-03-28 1997-03-20 Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen

Country Status (9)

Country Link
US (1) US5734187A (enExample)
JP (1) JP4180659B2 (enExample)
KR (1) KR20000005093A (enExample)
CN (1) CN100388499C (enExample)
AU (1) AU2587097A (enExample)
DE (2) DE19781675T1 (enExample)
GB (1) GB2329281B (enExample)
RU (1) RU2156013C2 (enExample)
WO (1) WO1997036330A1 (enExample)

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US5917197A (en) * 1997-05-21 1999-06-29 Siemens Aktiengesellschaft Integrated multi-layer test pads
US6727170B2 (en) 1998-02-16 2004-04-27 Renesas Technology Corp. Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
JPH11233621A (ja) * 1998-02-16 1999-08-27 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP4214428B2 (ja) * 1998-07-17 2009-01-28 ソニー株式会社 半導体記憶装置
US6252291B1 (en) * 1998-09-28 2001-06-26 Agilent Technologies, Inc. Modifiable semiconductor circuit element
US6545359B1 (en) * 1998-12-18 2003-04-08 Semiconductor Energy Laboratory Co., Ltd. Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof
US6414367B1 (en) * 1999-10-28 2002-07-02 National Semiconductor Corporation Interconnect exhibiting reduced parasitic capacitance variation
US6862720B1 (en) 1999-10-28 2005-03-01 National Semiconductor Corporation Interconnect exhibiting reduced parasitic capacitance variation
US7283381B2 (en) 2000-08-17 2007-10-16 David Earl Butz System and methods for addressing a matrix incorporating virtual columns and addressing layers
US6462977B2 (en) 2000-08-17 2002-10-08 David Earl Butz Data storage device having virtual columns and addressing layers
US7170115B2 (en) * 2000-10-17 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method of producing the same
JP3467699B2 (ja) * 2001-03-26 2003-11-17 セイコーエプソン株式会社 半導体装置、メモリシステムおよび電子機器
JP2002359299A (ja) 2001-03-26 2002-12-13 Seiko Epson Corp 半導体装置、メモリシステムおよび電子機器
JP3656592B2 (ja) * 2001-03-26 2005-06-08 セイコーエプソン株式会社 半導体装置、メモリシステムおよび電子機器
US6806754B2 (en) 2001-07-19 2004-10-19 Micron Technology, Inc. Method and circuitry for reducing duty cycle distortion in differential delay lines
US6919639B2 (en) * 2002-10-15 2005-07-19 The Board Of Regents, The University Of Texas System Multiple copper vias for integrated circuit metallization and methods of fabricating same
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US20050247981A1 (en) * 2004-05-10 2005-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device having shielded access lines
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
US8454750B1 (en) 2005-04-26 2013-06-04 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US7606057B2 (en) * 2006-05-31 2009-10-20 Arm Limited Metal line layout in a memory cell
US10037905B2 (en) * 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US8465991B2 (en) * 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US20100267231A1 (en) * 2006-10-30 2010-10-21 Van Schravendijk Bart Apparatus for uv damage repair of low k films prior to copper barrier deposition
US7671422B2 (en) * 2007-05-04 2010-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pseudo 6T SRAM cell
JP5130596B2 (ja) * 2007-05-30 2013-01-30 国立大学法人東北大学 半導体装置
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
CN102130129B (zh) * 2010-01-20 2013-12-18 上海华虹Nec电子有限公司 Sram的版图结构及其制造方法
KR102178732B1 (ko) * 2013-12-20 2020-11-13 삼성전자주식회사 반도체 소자
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing

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JPH0770623B2 (ja) * 1988-07-08 1995-07-31 三菱電機株式会社 スタティックランダムアクセスメモリ装置
JP2503661B2 (ja) * 1989-06-28 1996-06-05 日本電気株式会社 半導体メモリ素子およびその製造方法
US5452247A (en) * 1989-12-20 1995-09-19 Fujitsu Limited Three-dimensional static random access memory device for avoiding disconnection among transistors of each memory cell
US5350933A (en) * 1990-02-21 1994-09-27 Sony Corporation Semiconductor CMOS static RAM with overlapping thin film transistors
US5343063A (en) * 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
JP3015186B2 (ja) * 1991-03-28 2000-03-06 三菱電機株式会社 半導体記憶装置とそのデータの読み出しおよび書き込み方法
US5298782A (en) * 1991-06-03 1994-03-29 Sgs-Thomson Microelectronics, Inc. Stacked CMOS SRAM cell with polysilicon transistor load
RU2007785C1 (ru) * 1991-06-28 1994-02-15 Камышный Алексей Николаевич Способ изменения проводимости канала исток - сток полевого транзистора
KR940009608B1 (ko) * 1991-11-30 1994-10-15 삼성전자 주식회사 반도체 메모리장치 및 그 제조방법
EP1154488B1 (en) * 1992-09-04 2003-05-07 Mitsubishi Denki Kabushiki Kaisha A semiconductor memory device
KR970001346B1 (ko) * 1992-10-12 1997-02-05 삼성전자 주식회사 반도체 메모리장치 및 그 제조방법
US5377139A (en) * 1992-12-11 1994-12-27 Motorola, Inc. Process forming an integrated circuit
JP2682393B2 (ja) * 1993-08-13 1997-11-26 日本電気株式会社 スタティック形半導体記憶装置
JP3285438B2 (ja) * 1993-10-29 2002-05-27 三菱電機株式会社 半導体記憶装置
JP3257887B2 (ja) * 1993-12-16 2002-02-18 三菱電機株式会社 半導体装置
JPH07176633A (ja) * 1993-12-20 1995-07-14 Nec Corp Ｃｍｏｓ型スタティックメモリ
JP2684979B2 (ja) * 1993-12-22 1997-12-03 日本電気株式会社 半導体集積回路装置及びその製造方法
US5409854A (en) * 1994-03-15 1995-04-25 National Semiconductor Corporation Method for forming a virtual-ground flash EPROM array with floating gates that are self aligned to the field oxide regions of the array
US5422296A (en) * 1994-04-25 1995-06-06 Motorola, Inc. Process for forming a static-random-access memory cell
JP3426711B2 (ja) * 1994-07-05 2003-07-14 株式会社日立製作所 半導体集積回路装置およびその製造方法

Also Published As

Publication number Publication date
WO1997036330A1 (en) 1997-10-02
HK1017136A1 (en) 1999-11-12
US5734187A (en) 1998-03-31
RU2156013C2 (ru) 2000-09-10
CN100388499C (zh) 2008-05-14
JP4180659B2 (ja) 2008-11-12
AU2587097A (en) 1997-10-17
CN1222254A (zh) 1999-07-07
GB2329281B (en) 2000-11-15
DE19781675B4 (de) 2006-08-24
JP2000507742A (ja) 2000-06-20
GB9820831D0 (en) 1998-11-18
KR20000005093A (ko) 2000-01-25
GB2329281A (en) 1999-03-17

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: H01L 27/11

8607 Notification of search results after publication
8607 Notification of search results after publication