DE69722837D1 - Speicheranordnung mit überlagerter Busstruktur - Google Patents

Speicheranordnung mit überlagerter Busstruktur

Info

Publication number
DE69722837D1
DE69722837D1 DE69722837T DE69722837T DE69722837D1 DE 69722837 D1 DE69722837 D1 DE 69722837D1 DE 69722837 T DE69722837 T DE 69722837T DE 69722837 T DE69722837 T DE 69722837T DE 69722837 D1 DE69722837 D1 DE 69722837D1
Authority
DE
Germany
Prior art keywords
bus structure
memory arrangement
superimposed bus
superimposed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69722837T
Other languages
English (en)
Other versions
DE69722837T2 (de
Inventor
Haruki Toda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69722837D1 publication Critical patent/DE69722837D1/de
Publication of DE69722837T2 publication Critical patent/DE69722837T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69722837T 1996-03-11 1997-03-11 Speicheranordnung mit überlagerter Busstruktur Expired - Lifetime DE69722837T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5281196 1996-03-11
JP5281196 1996-03-11

Publications (2)

Publication Number Publication Date
DE69722837D1 true DE69722837D1 (de) 2003-07-24
DE69722837T2 DE69722837T2 (de) 2004-05-13

Family

ID=12925238

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69722837T Expired - Lifetime DE69722837T2 (de) 1996-03-11 1997-03-11 Speicheranordnung mit überlagerter Busstruktur

Country Status (4)

Country Link
US (5) US5978300A (de)
KR (1) KR100268773B1 (de)
DE (1) DE69722837T2 (de)
TW (1) TW348266B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW348266B (en) * 1996-03-11 1998-12-21 Toshiba Co Ltd Semiconductor memory device
US6295231B1 (en) 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
JP2000137983A (ja) 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
JP2000100169A (ja) * 1998-09-22 2000-04-07 Fujitsu Ltd 半導体記憶装置及び半導体記憶装置のデータ制御方法
US6404694B2 (en) 1999-08-16 2002-06-11 Hitachi, Ltd. Semiconductor memory device with address comparing functions
US6530045B1 (en) * 1999-12-03 2003-03-04 Micron Technology, Inc. Apparatus and method for testing rambus DRAMs
JP4083944B2 (ja) 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
DE10034255C2 (de) * 2000-07-14 2002-05-16 Infineon Technologies Ag Schaltungsanordnung zum Lesen und Schreiben von Information an einem Speicherzellenfeld
EP1316955A1 (de) * 2001-11-30 2003-06-04 Infineon Technologies AG Zwischenspeichereinrichtung
US6917552B2 (en) * 2002-03-05 2005-07-12 Renesas Technology Corporation Semiconductor device using high-speed sense amplifier
DE10255867B3 (de) * 2002-11-29 2004-08-05 Infineon Technologies Ag Dynamischer RAM-Halbleiterspeicher und Verfahren zum Betrieb desselben
DE10258168B4 (de) * 2002-12-12 2005-07-07 Infineon Technologies Ag Integrierter DRAM-Halbleiterspeicher und Verfahren zum Betrieb desselben
JPWO2004075199A1 (ja) * 2003-02-18 2006-06-01 富士通株式会社 半導体記憶装置及び半導体記憶装置の読み出し方法
JP2007128633A (ja) * 2005-10-07 2007-05-24 Matsushita Electric Ind Co Ltd 半導体記憶装置及びこれを備えた送受信システム
EP3103511B1 (de) 2015-06-11 2019-03-06 Oticon A/s Cochlea-hörgerät mit kabelantenne

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
JPH03108188A (ja) * 1989-09-20 1991-05-08 Fujitsu Ltd 半導体記憶装置
US6223264B1 (en) * 1991-10-24 2001-04-24 Texas Instruments Incorporated Synchronous dynamic random access memory and data processing system using an address select signal
JP2962080B2 (ja) * 1991-12-27 1999-10-12 日本電気株式会社 ランダムアクセスメモリ
US5272664A (en) * 1993-04-21 1993-12-21 Silicon Graphics, Inc. High memory capacity DRAM SIMM
JPH0786425A (ja) * 1993-06-30 1995-03-31 Hitachi Ltd ダイナミック型ｒａｍ
JP3048498B2 (ja) * 1994-04-13 2000-06-05 株式会社東芝 半導体記憶装置
JP3176228B2 (ja) * 1994-08-23 2001-06-11 シャープ株式会社 半導体記憶装置
JP3135795B2 (ja) * 1994-09-22 2001-02-19 東芝マイクロエレクトロニクス株式会社 ダイナミック型メモリ
US5613084A (en) * 1994-10-04 1997-03-18 Panasonic Technologies, Inc. Interpolation filter selection circuit for sample rate conversion using phase quantization
JP3267462B2 (ja) * 1995-01-05 2002-03-18 株式会社東芝 半導体記憶装置
US5621695A (en) * 1995-07-17 1997-04-15 Galvantech, Inc. SRAM with simplified architecture for use with pipelined data
JPH09161476A (ja) * 1995-10-04 1997-06-20 Toshiba Corp 半導体メモリ及びそのテスト回路、並びにデ−タ転送システム
TW348266B (en) * 1996-03-11 1998-12-21 Toshiba Co Ltd Semiconductor memory device
US5671188A (en) * 1996-06-26 1997-09-23 Alliance Semiconductor Corporation Random access memory having selective intra-bank fast activation of sense amplifiers

Also Published As

Publication number Publication date
KR100268773B1 (ko) 2000-10-16
DE69722837T2 (de) 2004-05-13
TW348266B (en) 1998-12-21
US20010005336A1 (en) 2001-06-28
US6469951B2 (en) 2002-10-22
US6219295B1 (en) 2001-04-17
KR970067854A (ko) 1997-10-13
US6396765B2 (en) 2002-05-28
US20020067653A1 (en) 2002-06-06
US5978300A (en) 1999-11-02
US6084817A (en) 2000-07-04

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Legal Events

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8364 No opposition during term of opposition