DE69914142D1 - Halbleiteranordnung mit einer speicherzelle - Google Patents

Halbleiteranordnung mit einer speicherzelle

Info

Publication number
DE69914142D1
DE69914142D1 DE69914142T DE69914142T DE69914142D1 DE 69914142 D1 DE69914142 D1 DE 69914142D1 DE 69914142 T DE69914142 T DE 69914142T DE 69914142 T DE69914142 T DE 69914142T DE 69914142 D1 DE69914142 D1 DE 69914142D1
Authority
DE
Germany
Prior art keywords
storage cell
semiconductor arrangement
semiconductor
arrangement
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69914142T
Other languages
English (en)
Other versions
DE69914142T2 (de
Inventor
Der Sanden G Van
Geloven A Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69914142D1 publication Critical patent/DE69914142D1/de
Publication of DE69914142T2 publication Critical patent/DE69914142T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
DE69914142T 1998-03-18 1999-02-25 Halbleiteranordnung mit einer speicherzelle Expired - Lifetime DE69914142T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP98200866 1998-03-18
EP98200866 1998-03-18
PCT/IB1999/000331 WO1999048100A2 (en) 1998-03-18 1999-02-25 Semi-conductor device with a memory cell

Publications (2)

Publication Number Publication Date
DE69914142D1 true DE69914142D1 (de) 2004-02-19
DE69914142T2 DE69914142T2 (de) 2004-10-28

Family

ID=8233480

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69914142T Expired - Lifetime DE69914142T2 (de) 1998-03-18 1999-02-25 Halbleiteranordnung mit einer speicherzelle

Country Status (6)

Country Link
US (1) US5999442A (de)
EP (1) EP0983593B1 (de)
JP (1) JP2001527682A (de)
KR (1) KR100599130B1 (de)
DE (1) DE69914142T2 (de)
WO (1) WO1999048100A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181621B1 (en) * 1999-12-10 2001-01-30 Cypress Semiconductor Corp. Threshold voltage mismatch compensated sense amplifier for SRAM memory arrays
DE10031173C1 (de) * 2000-06-27 2002-01-24 Siemens Ag Verfahren zum Steuern einer Brennkraftmaschine
US6621726B2 (en) * 2001-11-13 2003-09-16 Intel Corporation Biasing technique for a high density SRAM
US6838723B2 (en) 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US7224024B2 (en) 2002-08-29 2007-05-29 Micron Technology, Inc. Single transistor vertical memory gain cell
US20040090820A1 (en) * 2002-11-08 2004-05-13 Saroj Pathak Low standby power SRAM
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7030436B2 (en) 2002-12-04 2006-04-18 Micron Technology, Inc. Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means
US6934181B2 (en) * 2003-02-06 2005-08-23 International Business Machines Corporation Reducing sub-threshold leakage in a memory array
JP4330516B2 (ja) * 2004-08-04 2009-09-16 パナソニック株式会社 半導体記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3662356A (en) * 1970-08-28 1972-05-09 Gen Electric Integrated circuit bistable memory cell using charge-pumped devices
US3870901A (en) * 1973-12-10 1975-03-11 Gen Instrument Corp Method and apparatus for maintaining the charge on a storage node of a mos circuit
US4805148A (en) * 1985-11-22 1989-02-14 Diehl Nagle Sherra E High impendance-coupled CMOS SRAM for improved single event immunity
JPH0745077A (ja) * 1993-08-02 1995-02-14 Nec Corp 記憶装置
US5708509A (en) * 1993-11-09 1998-01-13 Asahi Kogaku Kogyo Kabushiki Kaisha Digital data processing device
JP3085073B2 (ja) * 1994-01-24 2000-09-04 富士通株式会社 スタティックｒａｍ
JPH09282885A (ja) * 1996-04-11 1997-10-31 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0983593B1 (de) 2004-01-14
DE69914142T2 (de) 2004-10-28
WO1999048100A2 (en) 1999-09-23
WO1999048100A3 (en) 1999-11-18
KR20010012678A (ko) 2001-02-26
EP0983593A2 (de) 2000-03-08
US5999442A (en) 1999-12-07
JP2001527682A (ja) 2001-12-25
KR100599130B1 (ko) 2006-07-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

R082 Change of representative

Ref document number: 983593

Country of ref document: EP

Representative=s name: MUELLER-BORE & PARTNER PATENTANWAELTE, EUROPEA, DE