DE1564136C3 - Verfahren zum Herstellen von Halbleiterbauelementen - Google Patents

Verfahren zum Herstellen von Halbleiterbauelementen

Info

Publication number
DE1564136C3
DE1564136C3 DE1564136A DE1564136A DE1564136C3 DE 1564136 C3 DE1564136 C3 DE 1564136C3 DE 1564136 A DE1564136 A DE 1564136A DE 1564136 A DE1564136 A DE 1564136A DE 1564136 C3 DE1564136 C3 DE 1564136C3
Authority
DE
Germany
Prior art keywords
layer
emitter
semiconductor
insulating layer
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1564136A
Other languages
German (de)
English (en)
Other versions
DE1564136B2 (de
DE1564136A1 (de
Inventor
Frederick Hayes Putnam Valley N.Y. Dill Jun. (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US446780A external-priority patent/US3398335A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE1564136A1 publication Critical patent/DE1564136A1/de
Publication of DE1564136B2 publication Critical patent/DE1564136B2/de
Application granted granted Critical
Publication of DE1564136C3 publication Critical patent/DE1564136C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
DE1564136A 1965-03-31 1966-03-24 Verfahren zum Herstellen von Halbleiterbauelementen Expired DE1564136C3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US446780A US3398335A (en) 1965-03-31 1965-03-31 Transistor structure with an emitter region epitaxially grown over the base region
US73418568A 1968-03-18 1968-03-18

Publications (3)

Publication Number Publication Date
DE1564136A1 DE1564136A1 (de) 1969-09-25
DE1564136B2 DE1564136B2 (de) 1974-04-04
DE1564136C3 true DE1564136C3 (de) 1974-10-31

Family

ID=27034741

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1564136A Expired DE1564136C3 (de) 1965-03-31 1966-03-24 Verfahren zum Herstellen von Halbleiterbauelementen

Country Status (6)

Country Link
US (1) US3579814A (https=)
CH (1) CH446537A (https=)
DE (1) DE1564136C3 (https=)
GB (1) GB1061506A (https=)
NL (1) NL6602298A (https=)
SE (1) SE319836B (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3742490A (en) * 1970-10-12 1973-06-26 H Henderson Display system having flexible gear
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
US5059544A (en) * 1988-07-14 1991-10-22 International Business Machines Corp. Method of forming bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy
US5688474A (en) * 1993-06-01 1997-11-18 Eduardo E. Wolf Device for treating gases using microfabricated matrix of catalyst
CN108155098B (zh) * 2017-12-21 2020-08-18 安徽安芯电子科技股份有限公司 双极晶体管的制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189973A (en) * 1961-11-27 1965-06-22 Bell Telephone Labor Inc Method of fabricating a semiconductor device
NL302804A (https=) * 1962-08-23 1900-01-01
US3237271A (en) * 1963-08-07 1966-03-01 Bell Telephone Labor Inc Method of fabricating semiconductor devices

Also Published As

Publication number Publication date
DE1564136B2 (de) 1974-04-04
DE1564136A1 (de) 1969-09-25
GB1061506A (en) 1967-03-15
NL6602298A (https=) 1966-10-03
SE319836B (https=) 1970-01-26
CH446537A (de) 1967-11-15
US3579814A (en) 1971-05-25

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
E77 Valid patent as to the heymanns-index 1977
EHJ Ceased/non-payment of the annual fee