DE112022002544T5 - E/a-schaltung, halbleitervorrichtung, zellenbibliothek und verfahren zum entwerfen der schaltung einer halbleitervorrichtung - Google Patents
E/a-schaltung, halbleitervorrichtung, zellenbibliothek und verfahren zum entwerfen der schaltung einer halbleitervorrichtung Download PDFInfo
- Publication number
- DE112022002544T5 DE112022002544T5 DE112022002544.1T DE112022002544T DE112022002544T5 DE 112022002544 T5 DE112022002544 T5 DE 112022002544T5 DE 112022002544 T DE112022002544 T DE 112022002544T DE 112022002544 T5 DE112022002544 T5 DE 112022002544T5
- Authority
- DE
- Germany
- Prior art keywords
- power line
- circuit
- protection element
- buffer
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3953—Routing detailed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/38—Circuit design at the mixed level of analogue and digital signals
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Computer Networks & Wireless Communication (AREA)
- Architecture (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021-117798 | 2021-07-16 | ||
| JP2021117798 | 2021-07-16 | ||
| PCT/JP2022/023609 WO2023286506A1 (ja) | 2021-07-16 | 2022-06-13 | I/o回路、半導体装置、セルライブラリ、半導体装置の回路設計方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE112022002544T5 true DE112022002544T5 (de) | 2024-02-29 |
Family
ID=84919227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE112022002544.1T Pending DE112022002544T5 (de) | 2021-07-16 | 2022-06-13 | E/a-schaltung, halbleitervorrichtung, zellenbibliothek und verfahren zum entwerfen der schaltung einer halbleitervorrichtung |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20240119215A1 (https=) |
| JP (1) | JPWO2023286506A1 (https=) |
| CN (1) | CN117546281A (https=) |
| DE (1) | DE112022002544T5 (https=) |
| WO (1) | WO2023286506A1 (https=) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010028126A (ja) | 2009-09-14 | 2010-02-04 | Renesas Technology Corp | 半導体装置、セルライブラリおよび半導体集積回路の設計方法 |
| JP2010192932A (ja) | 2010-05-07 | 2010-09-02 | Panasonic Corp | 標準セル、標準セルライブラリおよび半導体集積回路 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04267542A (ja) * | 1991-02-22 | 1992-09-24 | Fujitsu Ltd | 半導体集積回路のレイアウト方法および装置 |
| JPH05175432A (ja) * | 1991-06-24 | 1993-07-13 | Hitachi Ltd | 半導体装置 |
| JPH11214521A (ja) * | 1998-01-22 | 1999-08-06 | Mitsubishi Electric Corp | 半導体集積回路および半導体集積回路の製造方法 |
| JP2000106419A (ja) * | 1998-09-29 | 2000-04-11 | Oki Electric Ind Co Ltd | Ic設計用ライブラリ及びレイアウトパターン設計方法 |
| JP3372918B2 (ja) * | 1999-12-21 | 2003-02-04 | 日本電気株式会社 | 設計支援システム及びセル配置方法 |
| JP3672912B2 (ja) * | 2003-01-20 | 2005-07-20 | Necマイクロシステム株式会社 | 半導体集積回路の自動レイアウト方法、及び半導体集積回路の自動レイアウトプログラム |
| JP4978998B2 (ja) * | 2004-03-12 | 2012-07-18 | ローム株式会社 | 半導体装置 |
| JP2009081293A (ja) * | 2007-09-26 | 2009-04-16 | Oki Semiconductor Co Ltd | 半導体チップ、及び複数の半導体チップが搭載された半導体装置 |
| JP2013021249A (ja) * | 2011-07-14 | 2013-01-31 | Toshiba Corp | 半導体集積装置 |
| JP2014241497A (ja) * | 2013-06-11 | 2014-12-25 | ローム株式会社 | 半導体集積回路 |
| WO2018180010A1 (ja) * | 2017-03-29 | 2018-10-04 | 株式会社ソシオネクスト | 半導体集積回路装置 |
-
2022
- 2022-06-13 JP JP2023535183A patent/JPWO2023286506A1/ja active Pending
- 2022-06-13 CN CN202280044122.3A patent/CN117546281A/zh active Pending
- 2022-06-13 DE DE112022002544.1T patent/DE112022002544T5/de active Pending
- 2022-06-13 WO PCT/JP2022/023609 patent/WO2023286506A1/ja not_active Ceased
-
2023
- 2023-12-19 US US18/545,662 patent/US20240119215A1/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010028126A (ja) | 2009-09-14 | 2010-02-04 | Renesas Technology Corp | 半導体装置、セルライブラリおよび半導体集積回路の設計方法 |
| JP2010192932A (ja) | 2010-05-07 | 2010-09-02 | Panasonic Corp | 標準セル、標準セルライブラリおよび半導体集積回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20240119215A1 (en) | 2024-04-11 |
| WO2023286506A1 (ja) | 2023-01-19 |
| JPWO2023286506A1 (https=) | 2023-01-19 |
| CN117546281A (zh) | 2024-02-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R012 | Request for examination validly filed | ||
| R079 | Amendment of ipc main class |
Free format text: PREVIOUS MAIN CLASS: H01L0021822000 Ipc: H10D0089100000 |
|
| R016 | Response to examination communication |