WO2023286506A1 - Ｉ／ｏ回路、半導体装置、セルライブラリ、半導体装置の回路設計方法 - Google Patents

Ｉ／ｏ回路、半導体装置、セルライブラリ、半導体装置の回路設計方法 Download PDF

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Publication number
WO2023286506A1
WO2023286506A1 PCT/JP2022/023609 JP2022023609W WO2023286506A1 WO 2023286506 A1 WO2023286506 A1 WO 2023286506A1 JP 2022023609 W JP2022023609 W JP 2022023609W WO 2023286506 A1 WO2023286506 A1 WO 2023286506A1
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Prior art keywords
power supply
circuit
protection element
buffer
supply line
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Ceased
Application number
PCT/JP2022/023609
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English (en)
French (fr)
Japanese (ja)
Inventor
賢一 吉村
啓明 木村
友和 岡田
勇二 黒土
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to DE112022002544.1T priority Critical patent/DE112022002544T5/de
Priority to JP2023535183A priority patent/JPWO2023286506A1/ja
Priority to CN202280044122.3A priority patent/CN117546281A/zh
Publication of WO2023286506A1 publication Critical patent/WO2023286506A1/ja
Priority to US18/545,662 priority patent/US20240119215A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/38—Circuit design at the mixed level of analogue and digital signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules

Definitions

  • the invention disclosed in this specification relates to an I/O [input/output] circuit, a semiconductor device, a cell library, and a circuit design method for a semiconductor device.
  • Patent Documents 1 and 2 can be cited as conventional technologies related to the above.
  • an I/O circuit equipped with a protection system required when multiple circuits using different power supplies share a single pad can be formed by combining standard cells. I didn't.
  • the invention disclosed in this specification aims at forming an I/O circuit with a desired protection system by combining standard cells in view of the above-mentioned problems found by the inventors of the present application.
  • the I/O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and the multiple types of standard cells include at least a first standard cell and a second standard cell, wherein the first standard cell includes a first protection element and a first power supply formed in an upper region of the first protection element so as to be electrically connected to the first protection element; and a line, wherein the second standard cell is connected to a second protection element formed in the same layout as the first protection element and the second protection element while being disconnected from the first power supply line. and a second power line formed in an upper region of the second protection element.
  • FIG. 1 is a diagram showing a configuration example of an application using a semiconductor device.
  • FIG. 2 is a diagram showing a first comparative example of an I/O circuit.
  • FIG. 3 is a diagram showing a second comparative example of the I/O circuit.
  • FIG. 4 is a diagram showing a third comparative example of the I/O circuit.
  • FIG. 5 is a diagram showing a first embodiment of an I/O circuit.
  • FIG. 6 is a diagram showing a second embodiment of the I/O circuit.
  • FIG. 7 is a diagram showing a third embodiment of the I/O circuit.
  • FIG. 1 is a diagram showing a configuration example of an application using a semiconductor device.
  • the semiconductor device 100 of this configuration example is an in-vehicle integrated communication IC for receiving commands via an in-vehicle network and controlling controllers (ECU [electronic control unit], etc.) mounted in various terminal devices.
  • the semiconductor device 100 has a plurality of external terminals T1 to T5 as means for establishing electrical connection with the outside of the device.
  • the external terminal T1 is a power supply terminal that receives power supply from the battery.
  • the external terminals T2 to T4 are connected to various terminal devices (for example, the LED [light emitting diode] light emitting device 200, the motor device 300 and the switch device 400) using arbitrary protocols (I2C [inter-integrated circuit], SPI [serial peripheral interface], GPIO [general-purpose input/output] and PWM [pulse width modulation], etc.) is a communication terminal for transmitting and receiving signals.
  • the external terminal T5 is a network terminal connected to an arbitrary in-vehicle network (LIN [local interconnect network], CXPI [clock extension peripheral interface], CAN [controller area network], etc.).
  • the LED light emitting device 200 has an LED 210 and an LED driver IC 220 that receives commands from the semiconductor device 100 and controls the light emission drive of the LED 210 .
  • the motor device 300 has a motor 310 and a motor driver IC 320 that receives commands from the semiconductor device 100 and controls the rotation of the motor 310 .
  • the switch device 400 has a switch 410 and a switch monitor IC 420 that monitors the open/closed state of the switch 410 and notifies the semiconductor device 100 of the detection result.
  • the semiconductor device 100 of this configuration example has a power supply circuit 110, a digital circuit 120 (digital circuits 120A and 120B in this drawing), an analog circuit 130, an I/O circuit 140, and a power switch SW.
  • the power supply circuit 110 generates a predetermined internal power supply voltage from the battery voltage applied to the external terminal T1 and supplies it to each part of the semiconductor device 100 .
  • the circuit blocks integrated in the semiconductor device 100 belong to either the AO [always ON] area or the PSO [partial shut-OFF] area.
  • the power supply circuit 110 is mounted in the AO area.
  • the digital circuit 120A is one of the circuit blocks mounted in the AO area, and includes a power supply controller, low-speed oscillator, part of the test circuit, and so on.
  • the digital circuit 120B is one of the circuit blocks implemented in the PSO area, and includes a CPU [central processing unit], SRAM [static random access memory], high-speed oscillator, part of the test circuit, LIN/CAN/CXPI interface. interface, I2C/SPI interface, and GPIO interface.
  • the analog circuit 130 includes flash memory, DAC [digital-to-analog converter] and ADC [analog-to-digital]. Note that the analog circuit 130 may be mounted in the AO area or the PSO area.
  • the I/O circuit 140 is a front end that exchanges signals between the external terminals T1 to T5 and the internal circuits (power supply circuit 110, digital circuits 120A and 120B, and analog circuit 130). Note that the I/O circuits 140 may be arranged along the four sides of the semiconductor device 100 so as to surround the internal circuits described above in a plan view of the semiconductor device 100 .
  • the power switch SW connects/disconnects the power supply path from the power supply circuit 110 to the PSO area based on instructions from the digital circuit 120A (especially the power supply controller).
  • a schematic circuit diagram of the I/O circuit 140 is depicted on the left side of the figure.
  • a schematic circuit layout of the I/O circuit 140 in xy plan view is depicted.
  • the I/O circuit 140 of the first comparative example is formed by arbitrarily combining multiple types of standard cells included in the I/O cell library 10 .
  • the I/O cell library 10 is read from a circuit design program executed by a computer, and can be understood as a kind of database for circuit design.
  • the above multiple types of standard cells have their respective shapes and layouts so that even if one of the standard cells is replaced with another standard cell, there is no need to modify the surrounding standard cells. are standardized.
  • a circuit design method for the semiconductor device 100 (especially the I/O circuit 140) using the I/O cell library 10 will be briefly described. First, a step of selecting and arranging a plurality of types of standard cells included in the I/O cell library 10 and arbitrarily combining them is performed. Next, a step of laying power supply lines, signal lines, etc. is performed so as to connect the arbitrarily combined plural types of standard cells and other circuit blocks. Finally, a step of verifying whether the designed circuit satisfies desired conditions (electrical characteristics, etc.) is performed.
  • the same type of I/O cells 11X and 11Y and different types of I/O cells 11X and 11Y are used as the plurality of types of standard cells described above. are formed by combining the I/O cells 12 of
  • the I/O cell 11X includes a protection element 11Xa and an I/O buffer 11Xb.
  • the I/O cell 12 includes a protection element 12a and an I/O buffer 12b.
  • the I/O cell 11Y includes a protection element 11Ya and an I/O buffer 11Yb.
  • the protection element 11Xa includes electrostatic protection diodes D1 and D2.
  • Both the anode of the electrostatic protection diode D1 and the cathode of the electrostatic protection diode D2 are connected to the pad PAD1 via the wiring L1.
  • the protection element 12a includes electrostatic protection diodes D3 and D4.
  • Both the anode of the electrostatic protection diode D3 and the cathode of the electrostatic protection diode D4 are connected to the pad PAD1 via the wiring L2.
  • the protection element 11Ya includes electrostatic protection diodes D5 and D6.
  • Both the anode of the electrostatic protection diode D5 and the cathode of the electrostatic protection diode D6 are connected to the pad PAD2 via the wiring L3.
  • the I/O buffer 11Xb is an input buffer, an output buffer, or an input/output buffer formed to connect with the protection element 11Xa.
  • the I/O buffer 12b is an input buffer, an output buffer, or an input/output buffer formed to connect with the protection element 12a.
  • the I/O buffer 12b included in the I/O cell 12 is not used, and the protection element 12a and the analog circuit 31 are directly connected. Therefore, both the power supply node and the ground node of the I/O buffer 12b are open.
  • the I/O buffer 11Yb is an input buffer, an output buffer, or an input/output buffer formed to be connected to the protection element 11Ya.
  • the I/O cell 11X and the I/O cell 12 are commonly connected to the pad PAD1. Therefore, in the semiconductor device 100, the function of the pad PAD1 can be selectively used depending on the application.
  • the digital circuit 21 is connected to the pad PAD1 via the I/O cell 11X and operates by being supplied with the first power supply voltage VDDH.
  • the digital circuit 22 is connected to the pad PAD2 via the I/O cell 11Y and operates by being supplied with the first power supply voltage VDDH.
  • the analog circuit 31 is connected to the pad PAD1 via the I/O cell 12 and operates by being supplied with the first power supply voltage VDDH.
  • the digital circuits 21 and 22 described above can be understood as belonging to either of the previously described digital circuits 120A and 120B (FIG. 1).
  • Analog circuit 31 may also be understood as belonging to analog circuit 130 (FIG. 1) previously described.
  • I/O cells 11X, 11Y and 12 are each formed in the same rectangular shape in the xy plan view, and the protection elements 11Xa, 11Ya and 12a included therein are arranged in the same layout. ing.
  • the I/O buffers 11Xb, 11Yb and 12b are also arranged in the same layout.
  • the first power supply voltage VDDH is applied to both the protection element 11Xa and the I/O buffer 11Xb directly connected thereto.
  • the first power supply voltage VDDH is applied to both the protection element 12a and the analog circuit 31 (ignoring the unused I/O buffer 12b) directly connected thereto.
  • the first power supply voltage VDDH is applied to both the protection element 11Ya and the I/O buffer 11Yb directly connected thereto. Therefore, the above conditions are satisfied.
  • the I/O circuit 140 of the second comparative example is formed by combining I/O cells 13 , 14 and 15 as multiple types of standard cells included in the I/O cell library 10 .
  • the I/O cell 13 includes a protection element 13a and an I/O buffer 13b.
  • the I/O cell 14 includes a protection element 14a and a limiting resistor 14b.
  • the I/O cell 15 includes a protection element 15a and an I/O buffer 15b.
  • the protection element 13a includes an electrostatic protection diode D7.
  • the protection element 14a includes electrostatic protection diodes D8 and D9.
  • Both the anode of the electrostatic protection diode D8 and the cathode of the electrostatic protection diode D9 are connected to the pad PAD4 via the wiring L5.
  • the protection element 15a includes an electrostatic protection diode D10.
  • the pad PAD5 corresponds to a power supply pad to which the first power supply voltage VDDH is applied.
  • the I/O buffer 13b is an input buffer, an output buffer, or an input/output buffer formed to connect with the protection element 13a.
  • the I/O buffer 13b included in the I/O cell 13 is unused. Therefore, both the power supply node and the ground node of the I/O buffer 13b are open.
  • the limiting resistor 14b is a resistive element formed to be connected to the protective element 14a.
  • the I/O buffer 15b is an input buffer, an output buffer, or an input/output buffer formed to connect with the protection element 15a.
  • the I/O buffer 15b included in the I/O cell 15 is unused. Therefore, the power supply node and the ground node of the I/O buffer 15b are both open.
  • the analog circuit 32 is connected to the pad PAD4 via the I/O cell 14 and operates by being supplied with the first power supply voltage VDDH. Note that analog circuit 32 can be understood as belonging to analog circuit 130 (FIG. 1) previously described.
  • the I/O cells 13 to 15 are each formed in the same rectangular shape in the xy plan view, and the protection elements 13a to 15a included therein are arranged in the same layout. Also, the I/O buffer 13b, the limiting resistor 14b, and the I/O buffer 15b are arranged in the same layout.
  • I/O circuits 140 can be designed by arbitrarily combining the O-cells 12-15.
  • the third comparative example has basically the same configuration as the previously mentioned first comparative example (Fig. 2).
  • a single pad PAD1 is shared by both the digital circuit 21 and the analog circuit 31 (particularly those requiring high precision such as ADC), power supply noise caused by the operation of the digital circuits 21 and 22
  • the power supply systems of the digital circuits 21 and 22 and the analog circuit 31 be separated from each other so that the analog circuit 31 is not affected by the noise.
  • the digital circuits 21 and 22 are supplied with the previously mentioned first power supply voltage VDDH.
  • the first power supply voltage VDDH applied to the protection element 12a described above and the analog circuit 31 directly connected to the protection element 12a are applied to the first power supply voltage VDDH. is different from the applied second power supply voltage VDDA. That is, the circuit directly connected to the protection element 12a cannot satisfy the above-mentioned condition that it must operate using the same voltage as the power supply voltage applied to the protection element 12a.
  • the I/O cell library 10 described so far realizes the protection system required when, for example, the digital circuit 21 and the analog circuit 31 using different power supply voltages share a single pad PAD1. I can't.
  • an I/O circuit 140 having a desired protection system even when a single pad PAD1 is shared by the digital circuit 21 and the analog circuit 31 that use different power supply voltages. can be formed by combining standard cells.
  • FIG. 5 is a diagram illustrating a first embodiment of the I/O circuit 140. As shown in FIG. 2 to 4, a schematic circuit diagram of the I/O circuit 140 is depicted on the left side of the figure. On the other hand, on the right side of the drawing, a schematic circuit layout of the I/O circuit 140 in xy plan view is depicted.
  • the I/O cell 12A includes a protection element 12a and an I/O buffer 12b, like the I/O cell 12 described above.
  • the I/O cells 11X, 11Y and 12A are each formed in the same rectangular shape in the xy plan view, and the protection elements 11Xa, 11Ya and 12a included therein are arranged in the same layout. ing.
  • the I/O buffers 11Xb, 11Yb and 12b are also arranged in the same layout. In this regard, there is no difference from the first comparative example (FIG. 2).
  • the I/O cell 12A includes power supply lines L21 and L51 as its characteristic components.
  • the upper region of the I/O buffer 12b is used as the wiring region of the power supply line L51 necessary for changing the power connection destination of the protection element 12a from the first power supply voltage VDDH. ing. Therefore, it is possible to select the power connection destination of the protection element 12a without changing the circuit configuration and layout of the protection element 12a and the I/O buffer 12b.
  • the I/O circuit 140 of the first embodiment it is possible to apply the second power supply voltage VDDA different from the first power supply voltage VDDH to the protective element 12a.
  • both the protective element 12a and the analog circuit 31 can be supplied with the common second power supply voltage VDDA. Therefore, for example, when a single pad PAD1 is shared by the digital circuit 21 and the analog circuit 31 that use different power supply voltages, the circuit directly connected to the protection element 12a receives the same voltage as the power supply voltage applied to the protection element 12a. It is possible to satisfy the above-mentioned condition that the operation must be performed using
  • the novel I/O cell 12A is used, a separate protective element 40 (FIG. 4) is not required, unlike the third comparative example (FIG. 4). That is, the I/O circuit 140 of the first embodiment maintains an area equivalent to that of the I/O circuit 140 (FIG. 2) of the first comparative example having a single power supply system, while the analog circuit 31
  • the power system of the protection element 12a to be connected can be separated from the power systems of the other protection elements 11Xa and 11Ya.
  • the I/O buffer 12b cannot be used in the I/O cell 12A.
  • the connection destination of the I/O cell 12A is the analog circuit 31, the I/O buffer 12b is not required in the first place (see FIG. 2), so there is no particular problem.
  • a separate I/O buffer may be provided inside the digital circuit. Since the I/O buffer generally has a smaller area than the protective element, it is possible to suppress an increase in area compared to the third comparative example (FIG. 4) that requires a separate protective element 40 .
  • FIG. 6 is a diagram showing a second embodiment of the I/O circuit 140. As shown in FIG. 2 to 5, a schematic circuit diagram of the I/O circuit 140 is depicted on the left side of the figure. On the other hand, on the right side of the drawing, a schematic circuit layout of the I/O circuit 140 in xy plan view is depicted.
  • the I/O circuit 140 of the second embodiment is formed by using the I/O cells 12B in place of the I/O cells 12A while being based on the first embodiment (FIG. 5). It is
  • the I/O cell 12B has basically the same configuration as the I/O cell 12A described above, but further has a power supply line L31 and power supply lines L61 and L62 (see the large dashed lines in the figure).
  • the power lines L11 separated by the power line L21 can be brought into conduction by the power line L31 inside the I/O cell 12B. Therefore, the power supply line L11 connected to each of the I/O cells 11X and 11Y does not need to be reconnected outside the I/O cell 12B, thereby simplifying the wiring layout.
  • the power lines L61 and L62 are the same as described above. (equivalent to a wire). Referring to this figure, the power line L41 and the power line L61 are electrically connected through nodes n19 and n20 (contact holes, vias, etc.). Also, the power line L42 and the power line L62 are electrically connected through nodes n21 and n22 (contact holes, vias, or the like).
  • the power lines L41 and L42 separated by the power line L51 can be brought into conduction by the power lines L61 and L62, respectively, inside the I/O cell 12B. Therefore, the power supply lines L41 and L42 connected to the I/O cells 11X and 11Y need not be reconnected outside the I/O cell 12B, thus simplifying the wiring layout.
  • FIG. 7 is a diagram showing a third embodiment of the I/O circuit 140. As shown in FIG. 2 to 6, a schematic circuit diagram of the I/O circuit 140 is depicted on the left side of the figure. On the other hand, on the right side of the drawing, a schematic circuit layout of the I/O circuit 140 in xy plan view is depicted.
  • the I/O circuit 140 of the third embodiment is formed by using the I/O cell 12C instead of the I/O cell 12A while being based on the first embodiment (FIG. 5). It is
  • the I/O cell 12C has basically the same configuration as the previously described I/O cells 12A and 12B.
  • a non-wiring area is provided. That is, in the upper region of the I/O buffer 12b, the power supply lines L41 and L42 are partially removed, and the empty area is secured as it is as the laying area of the power supply line L51.
  • the power supply line L51 is not necessarily a component of the I/O cell 12C. It may be laid separately after that.
  • the I/O circuit disclosed in this specification is formed by arbitrarily combining multiple types of standard cells included in a cell library, and the multiple types of standard cells include at least a first standard cell and a second standard cell, wherein the first standard cell includes a first protection element and a first power supply formed in an upper region of the first protection element so as to be electrically connected to the first protection element; and a line, wherein the second standard cell is electrically connected to a second protection element formed in the same layout as the first protection element and the second protection element while being disconnected from the first power supply line. and a second power supply line formed in the upper region of the second protection element (first configuration).
  • the plurality of types of standard cells are arranged along the first direction, and the first power supply line is laid along the first direction.
  • a configuration (second configuration) may be used.
  • the second standard cell includes a third power line formed to be electrically connected to the first power line across the second power line. Further, a configuration (third configuration) may be employed.
  • the first standard cell includes a first buffer or a first resistor formed to be connected to the first protection element, and the first buffer or the first resistor. and a fourth power supply line formed in an upper region of the first resistor, wherein the second standard cell is formed to be connected to the second protection element in the same layout as the first buffer or the first resistor.
  • a configuration may further include a second buffer or a second resistor.
  • the upper region of the second buffer or the second resistor is formed so as to be disconnected from the fourth power supply line and electrically connected to the second power supply line.
  • the first buffer and the second buffer are respectively an input buffer, an output buffer, or an input/output buffer (sixth configuration).
  • the semiconductor device disclosed in this specification includes an I/O circuit having any one of the first to sixth configurations, and an I/O circuit connected to the first standard cell to supply power from the first power supply line. and a configuration (seventh configuration) having a first internal circuit configured to receive power from the second standard cell and a second internal circuit configured to be connected to the second standard cell and configured to receive power from the second power supply line It is
  • the semiconductor device according to the seventh configuration may further have a pad configured to commonly connect the first standard cell and the second standard cell (eighth configuration).
  • the cell library disclosed herein is a set of multiple types of standards that can be arbitrarily combined to form an I/O circuit of a semiconductor device by reading from a circuit design program executed by a computer.
  • the plurality of types of standard cells include at least a first standard cell and a second standard cell, the first standard cell being electrically connected to a first protection element and the first protection element; a first power supply line formed in an upper region of the first protection element in the second standard cell, wherein the second standard cell includes a second protection element formed in the same layout as the first protection element;
  • a configuration includes a second power supply line formed in an upper region of the second protection element so as to be electrically connected to the second protection element while being disconnected from one power supply line.
  • the semiconductor device circuit design method disclosed in the present specification uses the ninth cell library, and selects and arranges the plurality of types of standard cells included in the cell library. and laying power supply lines and signal lines so as to connect the arbitrarily combined standard cells and other circuit blocks (a tenth configuration); It is

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PCT/JP2022/023609 2021-07-16 2022-06-13 Ｉ／ｏ回路、半導体装置、セルライブラリ、半導体装置の回路設計方法 Ceased WO2023286506A1 (ja)

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DE112022002544.1T DE112022002544T5 (de) 2021-07-16 2022-06-13 E/a-schaltung, halbleitervorrichtung, zellenbibliothek und verfahren zum entwerfen der schaltung einer halbleitervorrichtung
JP2023535183A JPWO2023286506A1 (https=) 2021-07-16 2022-06-13
CN202280044122.3A CN117546281A (zh) 2021-07-16 2022-06-13 I/o电路、半导体装置、单元库和设计半导体装置的电路的方法
US18/545,662 US20240119215A1 (en) 2021-07-16 2023-12-19 I/o circuit, semiconductor device, cell library, and method of designing circuit of semiconductor device

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JP2021117798 2021-07-16

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* Cited by examiner, † Cited by third party
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JPH04267542A (ja) * 1991-02-22 1992-09-24 Fujitsu Ltd 半導体集積回路のレイアウト方法および装置
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