JPWO2023286506A1 - - Google Patents

Info

Publication number
JPWO2023286506A1
JPWO2023286506A1 JP2023535183A JP2023535183A JPWO2023286506A1 JP WO2023286506 A1 JPWO2023286506 A1 JP WO2023286506A1 JP 2023535183 A JP2023535183 A JP 2023535183A JP 2023535183 A JP2023535183 A JP 2023535183A JP WO2023286506 A1 JPWO2023286506 A1 JP WO2023286506A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023535183A
Other languages
Japanese (ja)
Other versions
JPWO2023286506A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023286506A1 publication Critical patent/JPWO2023286506A1/ja
Publication of JPWO2023286506A5 publication Critical patent/JPWO2023286506A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • G06F30/3953Routing detailed
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/38Circuit design at the mixed level of analogue and digital signals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/392Floor-planning or layout, e.g. partitioning or placement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00Details relating to CAD techniques
    • G06F2111/20Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2023535183A 2021-07-16 2022-06-13 Pending JPWO2023286506A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021117798 2021-07-16
PCT/JP2022/023609 WO2023286506A1 (ja) 2021-07-16 2022-06-13 I/o回路、半導体装置、セルライブラリ、半導体装置の回路設計方法

Publications (2)

Publication Number Publication Date
JPWO2023286506A1 true JPWO2023286506A1 (https=) 2023-01-19
JPWO2023286506A5 JPWO2023286506A5 (https=) 2024-04-11

Family

ID=84919227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023535183A Pending JPWO2023286506A1 (https=) 2021-07-16 2022-06-13

Country Status (5)

Country Link
US (1) US20240119215A1 (https=)
JP (1) JPWO2023286506A1 (https=)
CN (1) CN117546281A (https=)
DE (1) DE112022002544T5 (https=)
WO (1) WO2023286506A1 (https=)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04267542A (ja) * 1991-02-22 1992-09-24 Fujitsu Ltd 半導体集積回路のレイアウト方法および装置
JPH05175432A (ja) * 1991-06-24 1993-07-13 Hitachi Ltd 半導体装置
JPH11214521A (ja) * 1998-01-22 1999-08-06 Mitsubishi Electric Corp 半導体集積回路および半導体集積回路の製造方法
JP2000106419A (ja) * 1998-09-29 2000-04-11 Oki Electric Ind Co Ltd Ic設計用ライブラリ及びレイアウトパターン設計方法
JP3372918B2 (ja) * 1999-12-21 2003-02-04 日本電気株式会社 設計支援システム及びセル配置方法
JP3672912B2 (ja) * 2003-01-20 2005-07-20 Necマイクロシステム株式会社 半導体集積回路の自動レイアウト方法、及び半導体集積回路の自動レイアウトプログラム
JP4978998B2 (ja) * 2004-03-12 2012-07-18 ローム株式会社 半導体装置
JP2009081293A (ja) * 2007-09-26 2009-04-16 Oki Semiconductor Co Ltd 半導体チップ、及び複数の半導体チップが搭載された半導体装置
JP5159736B2 (ja) 2009-09-14 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置、セルライブラリおよび半導体集積回路の設計方法
JP2010192932A (ja) 2010-05-07 2010-09-02 Panasonic Corp 標準セル、標準セルライブラリおよび半導体集積回路
JP2013021249A (ja) * 2011-07-14 2013-01-31 Toshiba Corp 半導体集積装置
JP2014241497A (ja) * 2013-06-11 2014-12-25 ローム株式会社 半導体集積回路
WO2018180010A1 (ja) * 2017-03-29 2018-10-04 株式会社ソシオネクスト 半導体集積回路装置

Also Published As

Publication number Publication date
US20240119215A1 (en) 2024-04-11
WO2023286506A1 (ja) 2023-01-19
DE112022002544T5 (de) 2024-02-29
CN117546281A (zh) 2024-02-09

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Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231211

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250416