DE112013005837T5 - Halbleitervorrichtung mit einem vertikalen Mosfet mit Super-Junction-Struktur und Verfahren zur Herstellung davon - Google Patents
Halbleitervorrichtung mit einem vertikalen Mosfet mit Super-Junction-Struktur und Verfahren zur Herstellung davon Download PDFInfo
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- DE112013005837T5 DE112013005837T5 DE112013005837.5T DE112013005837T DE112013005837T5 DE 112013005837 T5 DE112013005837 T5 DE 112013005837T5 DE 112013005837 T DE112013005837 T DE 112013005837T DE 112013005837 T5 DE112013005837 T5 DE 112013005837T5
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thyristors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012268412 | 2012-12-07 | ||
JP2012268413A JP5724997B2 (ja) | 2012-12-07 | 2012-12-07 | スーパージャンクション構造の縦型mosfetを有する半導体装置の製造方法 |
JP2012-268412 | 2012-12-07 | ||
JP2012-268413 | 2012-12-07 | ||
JP2013-222256 | 2013-10-25 | ||
JP2013222256A JP5725129B2 (ja) | 2012-12-07 | 2013-10-25 | スーパージャンクション構造の縦型mosfetを有する半導体装置の製造方法 |
PCT/JP2013/007064 WO2014087633A1 (ja) | 2012-12-07 | 2013-12-03 | スーパージャンクション構造の縦型mosfetを有する半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE112013005837T5 true DE112013005837T5 (de) | 2015-08-20 |
Family
ID=50883075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE112013005837.5T Ceased DE112013005837T5 (de) | 2012-12-07 | 2013-12-03 | Halbleitervorrichtung mit einem vertikalen Mosfet mit Super-Junction-Struktur und Verfahren zur Herstellung davon |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN104838501B (ja) |
DE (1) | DE112013005837T5 (ja) |
WO (1) | WO2014087633A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015208097A1 (de) * | 2015-04-30 | 2016-11-03 | Infineon Technologies Ag | Herstellen einer Halbleitervorrichtung durch Epitaxie |
US11145745B2 (en) | 2018-07-18 | 2021-10-12 | Infineon Technologies Ag | Method for producing a semiconductor component |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108346581B (zh) * | 2018-02-08 | 2021-06-11 | 吉林华微电子股份有限公司 | 一种改善光刻标记对准的方法、用于光刻标记对准的外延层及超级结的制备方法 |
CN117810267B (zh) * | 2024-03-01 | 2024-04-30 | 深圳市冠禹半导体有限公司 | 一种栅极嵌埋式mosfet器件及其制造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5096739B2 (ja) * | 2006-12-28 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4844605B2 (ja) * | 2008-09-10 | 2011-12-28 | ソニー株式会社 | 半導体装置 |
JP5568856B2 (ja) * | 2008-11-13 | 2014-08-13 | 富士電機株式会社 | 半導体装置の製造方法 |
JP2010161114A (ja) * | 2009-01-06 | 2010-07-22 | Shin Etsu Handotai Co Ltd | 半導体素子の製造方法 |
JP2011216587A (ja) * | 2010-03-31 | 2011-10-27 | Renesas Electronics Corp | 半導体装置 |
CN101826554A (zh) * | 2010-05-04 | 2010-09-08 | 无锡新洁能功率半导体有限公司 | 具有超结结构的半导体器件及其制造方法 |
JP2013165197A (ja) * | 2012-02-13 | 2013-08-22 | Sumitomo Electric Ind Ltd | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
-
2013
- 2013-12-03 DE DE112013005837.5T patent/DE112013005837T5/de not_active Ceased
- 2013-12-03 WO PCT/JP2013/007064 patent/WO2014087633A1/ja active Application Filing
- 2013-12-03 CN CN201380063128.6A patent/CN104838501B/zh not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015208097A1 (de) * | 2015-04-30 | 2016-11-03 | Infineon Technologies Ag | Herstellen einer Halbleitervorrichtung durch Epitaxie |
US9647083B2 (en) | 2015-04-30 | 2017-05-09 | Infineon Technologies Austria Ag | Producing a semiconductor device by epitaxial growth |
US10243066B2 (en) | 2015-04-30 | 2019-03-26 | Infineon Technologies Austria Ag | Producing a semiconductor device by epitaxial growth |
DE102015208097B4 (de) | 2015-04-30 | 2022-03-31 | Infineon Technologies Ag | Herstellen einer Halbleitervorrichtung durch Epitaxie |
US11145745B2 (en) | 2018-07-18 | 2021-10-12 | Infineon Technologies Ag | Method for producing a semiconductor component |
Also Published As
Publication number | Publication date |
---|---|
CN104838501A (zh) | 2015-08-12 |
WO2014087633A1 (ja) | 2014-06-12 |
CN104838501B (zh) | 2017-07-11 |
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