DE10318283A1 - Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur - Google Patents

Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur Download PDF

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Publication number
DE10318283A1
DE10318283A1 DE10318283A DE10318283A DE10318283A1 DE 10318283 A1 DE10318283 A1 DE 10318283A1 DE 10318283 A DE10318283 A DE 10318283A DE 10318283 A DE10318283 A DE 10318283A DE 10318283 A1 DE10318283 A1 DE 10318283A1
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Germany
Prior art keywords
layer
strained
substrate
layers
silicon
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10318283A
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German (de)
English (en)
Inventor
Siegfried Prof. Dr. Mantl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
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Forschungszentrum Juelich GmbH
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Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Priority to DE10318283A priority Critical patent/DE10318283A1/de
Priority to PCT/DE2004/000736 priority patent/WO2004095552A2/de
Priority to US10/554,074 priority patent/US7615471B2/en
Priority to EP04726422A priority patent/EP1616345A2/de
Priority to JP2006504293A priority patent/JP5259954B2/ja
Publication of DE10318283A1 publication Critical patent/DE10318283A1/de
Priority to US12/496,676 priority patent/US7915148B2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
DE10318283A 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur Withdrawn DE10318283A1 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE10318283A DE10318283A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
PCT/DE2004/000736 WO2004095552A2 (de) 2003-04-22 2004-04-08 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur
US10/554,074 US7615471B2 (en) 2003-04-22 2004-04-08 Method for producing a tensioned layer on a substrate, and a layer structure
EP04726422A EP1616345A2 (de) 2003-04-22 2004-04-08 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur
JP2006504293A JP5259954B2 (ja) 2003-04-22 2004-04-08 基板上に歪層を製造する方法と層構造
US12/496,676 US7915148B2 (en) 2003-04-22 2009-07-02 Method of producing a tensioned layer on a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10318283A DE10318283A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur

Publications (1)

Publication Number Publication Date
DE10318283A1 true DE10318283A1 (de) 2004-11-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE10318283A Withdrawn DE10318283A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur

Country Status (5)

Country Link
US (2) US7615471B2 (enExample)
EP (1) EP1616345A2 (enExample)
JP (1) JP5259954B2 (enExample)
DE (1) DE10318283A1 (enExample)
WO (1) WO2004095552A2 (enExample)

Cited By (4)

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EP1816672A1 (de) * 2006-02-02 2007-08-08 Siltronic AG Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur
DE102006010273A1 (de) * 2006-03-02 2007-09-13 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte und Schichtstapel
US8404562B2 (en) 2010-09-30 2013-03-26 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
US8822306B2 (en) 2010-09-30 2014-09-02 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core

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DE10318284A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7202145B2 (en) * 2004-06-03 2007-04-10 Taiwan Semiconductor Manufacturing Company Strained Si formed by anneal
DE102004048096A1 (de) * 2004-09-30 2006-04-27 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
US8105908B2 (en) 2005-06-23 2012-01-31 Applied Materials, Inc. Methods for forming a transistor and modulating channel stress
KR100673020B1 (ko) 2005-12-20 2007-01-24 삼성전자주식회사 전계효과 소오스/드레인 영역을 가지는 반도체 장치
US7339230B2 (en) * 2006-01-09 2008-03-04 International Business Machines Corporation Structure and method for making high density mosfet circuits with different height contact lines
US7494886B2 (en) 2007-01-12 2009-02-24 International Business Machines Corporation Uniaxial strain relaxation of biaxial-strained thin films using ion implantation
US8471307B2 (en) * 2008-06-13 2013-06-25 Texas Instruments Incorporated In-situ carbon doped e-SiGeCB stack for MOS transistor
DE102008035816B4 (de) 2008-07-31 2011-08-25 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG, 01109 Leistungssteigerung in PMOS- und NMOS-Transistoren durch Verwendung eines eingebetteten verformten Halbleitermaterials
TWI430338B (zh) * 2008-10-30 2014-03-11 Corning Inc 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置
US8003491B2 (en) * 2008-10-30 2011-08-23 Corning Incorporated Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US9059201B2 (en) * 2010-04-28 2015-06-16 Acorn Technologies, Inc. Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
US8361889B2 (en) * 2010-07-06 2013-01-29 International Business Machines Corporation Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
DE102010064290B3 (de) * 2010-12-28 2012-04-19 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verformungserhöhung in Transistoren mit einem eingebetteten verformungsinduzierenden Halbleitermaterial durch Kondensation der legierungsbildenden Substanz
US8859348B2 (en) * 2012-07-09 2014-10-14 International Business Machines Corporation Strained silicon and strained silicon germanium on insulator
EP2741320B1 (en) * 2012-12-05 2020-06-17 IMEC vzw Manufacturing method of a finfet device with dual-strained channels
FR3003686B1 (fr) * 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
US9269714B2 (en) * 2013-06-10 2016-02-23 Globalfoundries Inc. Device including a transistor having a stressed channel region and method for the formation thereof
FR3041146B1 (fr) * 2015-09-11 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de mise en tension d'un film semi-conducteur
US9871057B2 (en) * 2016-03-03 2018-01-16 Globalfoundries Inc. Field-effect transistors with a non-relaxed strained channel
FR3050569B1 (fr) * 2016-04-26 2018-04-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Fabrication amelioree de silicium contraint en tension sur isolant par amorphisation puis recristallisation
WO2018004527A1 (en) * 2016-06-28 2018-01-04 Intel Corporation Cell for n-negative differential resistance (ndr) latch
US9818875B1 (en) * 2016-10-17 2017-11-14 International Business Machines Corporation Approach to minimization of strain loss in strained fin field effect transistors
CN111785679A (zh) * 2020-07-29 2020-10-16 联合微电子中心有限责任公司 半导体器件及其制备方法

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DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1816672A1 (de) * 2006-02-02 2007-08-08 Siltronic AG Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur
US8383495B2 (en) 2006-02-02 2013-02-26 Siltronic Ag Semiconductor layer structure and method for fabricating a semiconductor layer structure
US8829532B2 (en) 2006-02-02 2014-09-09 Siltronic Ag Semiconductor layer structure comprising a cavity layer and method for fabricating the semiconductor layer structure
DE102006010273A1 (de) * 2006-03-02 2007-09-13 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte und Schichtstapel
DE102006010273B4 (de) * 2006-03-02 2010-04-15 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung
US8404562B2 (en) 2010-09-30 2013-03-26 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
US8822306B2 (en) 2010-09-30 2014-09-02 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
US9224633B2 (en) 2010-09-30 2015-12-29 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
US9252045B2 (en) 2010-09-30 2016-02-02 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core
US9576844B2 (en) 2010-09-30 2017-02-21 Infineon Technologies Ag Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core
DE102011054035B4 (de) * 2010-09-30 2020-08-20 Infineon Technologies Ag Ein Verfahren zum Herstellen eines Verbundwafers mit einem Graphitkern und ein Verbundwafer mit einem Graphitkern

Also Published As

Publication number Publication date
WO2004095552A3 (de) 2004-12-02
WO2004095552A2 (de) 2004-11-04
US20060220127A1 (en) 2006-10-05
EP1616345A2 (de) 2006-01-18
JP5259954B2 (ja) 2013-08-07
US7615471B2 (en) 2009-11-10
US7915148B2 (en) 2011-03-29
US20090298301A1 (en) 2009-12-03
JP2006524426A (ja) 2006-10-26

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