DE10261460A1 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung

Info

Publication number
DE10261460A1
DE10261460A1 DE10261460A DE10261460A DE10261460A1 DE 10261460 A1 DE10261460 A1 DE 10261460A1 DE 10261460 A DE10261460 A DE 10261460A DE 10261460 A DE10261460 A DE 10261460A DE 10261460 A1 DE10261460 A1 DE 10261460A1
Authority
DE
Germany
Prior art keywords
film
electrode
plating solution
metal deposition
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10261460A
Other languages
German (de)
English (en)
Inventor
Yoshihiko Nemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10261460A1 publication Critical patent/DE10261460A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor

Landscapes

  • Chemically Coating (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE10261460A 2002-05-20 2002-12-31 Halbleitervorrichtung Ceased DE10261460A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002145333A JP2003338516A (ja) 2002-05-20 2002-05-20 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE10261460A1 true DE10261460A1 (de) 2003-12-11

Family

ID=29417113

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10261460A Ceased DE10261460A1 (de) 2002-05-20 2002-12-31 Halbleitervorrichtung

Country Status (4)

Country Link
US (1) US6686660B2 (https=)
JP (1) JP2003338516A (https=)
KR (1) KR100503940B1 (https=)
DE (1) DE10261460A1 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005265720A (ja) * 2004-03-19 2005-09-29 Nec Corp 電気接点構造及びその形成方法と素子検査方法
CN100468674C (zh) * 2004-11-25 2009-03-11 日本电气株式会社 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
US8653657B2 (en) * 2005-08-23 2014-02-18 Rohm Co., Ltd. Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
JP2007184381A (ja) * 2006-01-06 2007-07-19 Matsushita Electric Ind Co Ltd フリップチップ実装用回路基板とその製造方法、並びに半導体装置とその製造方法
JP2007243031A (ja) * 2006-03-10 2007-09-20 Seiko Epson Corp 配線基板の製造方法
KR100771675B1 (ko) * 2006-03-30 2007-11-01 엘지전자 주식회사 패키지용 인쇄회로기판 및 그 제조방법
US7538429B2 (en) * 2006-08-21 2009-05-26 Intel Corporation Method of enabling solder deposition on a substrate and electronic package formed thereby
US20080136019A1 (en) * 2006-12-11 2008-06-12 Johnson Michael E Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications
US8555494B2 (en) * 2007-10-01 2013-10-15 Intel Corporation Method of manufacturing coreless substrate
US8058726B1 (en) 2008-05-07 2011-11-15 Amkor Technology, Inc. Semiconductor device having redistribution layer
US9543262B1 (en) 2009-08-18 2017-01-10 Cypress Semiconductor Corporation Self aligned bump passivation
US8455361B2 (en) * 2010-01-07 2013-06-04 Texas Instruments Incorporated Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8552557B1 (en) 2011-12-15 2013-10-08 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8664090B1 (en) 2012-04-16 2014-03-04 Amkor Technology, Inc. Electronic component package fabrication method
US9245862B1 (en) 2013-02-12 2016-01-26 Amkor Technology, Inc. Electronic component package fabrication method and structure
JP5893225B2 (ja) * 2014-01-20 2016-03-23 三菱電機株式会社 半導体素子およびその製造方法、ならびに半導体装置
JP6406975B2 (ja) * 2014-10-24 2018-10-17 三菱電機株式会社 半導体素子および半導体装置
JP2017069381A (ja) 2015-09-30 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP2018137290A (ja) * 2017-02-20 2018-08-30 トヨタ自動車株式会社 半導体装置
JP7235541B2 (ja) 2019-03-11 2023-03-08 株式会社東芝 半導体装置およびその製造方法
US12417971B2 (en) * 2021-11-22 2025-09-16 Samsung Electronics Co., Ltd. Semiconductor package with multilayer bonding pads

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02276249A (ja) 1989-04-18 1990-11-13 Seiko Epson Corp 半導体回路バンプの製造方法
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
JPH1140745A (ja) 1997-07-17 1999-02-12 Hitachi Ltd 半導体装置およびその半導体装置を組み込んだ電子装置
JPH11214421A (ja) 1997-10-13 1999-08-06 Matsushita Electric Ind Co Ltd 半導体素子の電極形成方法

Also Published As

Publication number Publication date
KR20030090489A (ko) 2003-11-28
US20030214038A1 (en) 2003-11-20
JP2003338516A (ja) 2003-11-28
KR100503940B1 (ko) 2005-07-26
US6686660B2 (en) 2004-02-03

Similar Documents

Publication Publication Date Title
DE10261460A1 (de) Halbleitervorrichtung
DE2839234C2 (https=)
DE3330068C2 (https=)
DE3885834T2 (de) Lötstelle und Verfahren zu ihrer Bewerkstelligung.
DE19581952B4 (de) Verfahren zum Entfernen von Metallschichten von einer Pb/Sn-Lötbumps aufweisenden Substratoberfläche
DE69534543T2 (de) Halbleiteranordnung, Montagesubstrat für die Halbleiteranordnung und Verfahren zum Ersetzen der Halbleiteranordnung
DE69915299T2 (de) Methode um lötzinn auf eine anordnung zu übertragen und/oder die anordnung zu testen
EP2973671B1 (de) Verfahren zum herstellen eines elektronischen bauteils
DE3016132C2 (de) Verfahren zur Herstellung von gegen Hitzeschockeinwirkung widerstandsfähigen gedruckten Schaltungen
DE2554691C2 (de) Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung
DE102006012322A1 (de) Substrat für eine elektronische Einheit und Verfahren zu deren Herstellung, elektronische Einheit und Verfahren zu deren Herstellung
DE4313980B4 (de) Integrierte Hybridschaltung und Verfahren zu deren Herstellung
DE69215377T2 (de) Aufschmeltzlötsverfahren zum bilden von einem löthocker auf einer printplatte
DE69620273T2 (de) Verfahren zur Herstellung von Abstandshaltern auf einer elektrischen Leiterplatte
DE1943519A1 (de) Halbleiterbauelement
DE102018214495A1 (de) Spulenkomponente und mit einer spulenkomponente ausgestattetes befestigungssubstrat
DE3700912C2 (https=)
DE10146353B4 (de) Verfahren zur Herstellung einer Lötperle und Lötperlenstruktur
DE2658532C2 (de) Zwischenträger zur Halterung und Kontaktierung eines Halbleiterkörpers und Verfahren zu dessen Herstellung
DE19622971A1 (de) Halbleitereinrichtung zur Oberflächenmontage und Halbleitereinrichtungs-Montagekomponente sowie Verfahren zu ihrer Herstellung
DE102007057370A1 (de) Elektronisches Bauelement
EP1163827A1 (de) Verfahren zum erzeugen von lötfähigen und funktionellen oberflächen auf schaltungsträgern
DE102012111472A1 (de) Elektrodenpad, gedruckte Leiterplatte mit einem Elektrodenpad und Verfahren zur Herstellung einer gedruckten Leiterplatte
DE102009023629B4 (de) Leiterplatte und Herstellungsverfahren
DE10222670A1 (de) Elektrische Vorrichtung, welche eine Metallkontaktstelle besitzt, auf die eine Metallverdrahtung gebondet ist, und ein Herstellungsverfahren davon

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection