DE102019209889A1 - Verfahren zur Leiterplattenherstellung sowie gemäß dem Verfahren hergestellte Leiterplatten - Google Patents
Verfahren zur Leiterplattenherstellung sowie gemäß dem Verfahren hergestellte Leiterplatten Download PDFInfo
- Publication number
- DE102019209889A1 DE102019209889A1 DE102019209889.4A DE102019209889A DE102019209889A1 DE 102019209889 A1 DE102019209889 A1 DE 102019209889A1 DE 102019209889 A DE102019209889 A DE 102019209889A DE 102019209889 A1 DE102019209889 A1 DE 102019209889A1
- Authority
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- Germany
- Prior art keywords
- substrate
- metal layer
- cover metal
- conductor structure
- substrate side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 239000004020 conductor Substances 0.000 claims abstract description 90
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 229910052786 argon Inorganic materials 0.000 claims 1
- 239000001307 helium Substances 0.000 claims 1
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 101100201843 Cyprinus carpio rsph1 gene Proteins 0.000 description 1
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- 229910045601 alloy Inorganic materials 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 239000000788 chromium alloy Substances 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 239000011151 fibre-reinforced plastic Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910000623 nickel–chromium alloy Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
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- 238000007704 wet chemistry method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0585—Second resist used as mask for selective stripping of first resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102019209889.4A DE102019209889A1 (de) | 2019-07-04 | 2019-07-04 | Verfahren zur Leiterplattenherstellung sowie gemäß dem Verfahren hergestellte Leiterplatten |
| US17/624,082 US20220361341A1 (en) | 2019-07-04 | 2020-06-18 | Method of producing printed circuit boards and printed circuit boards produced in accordance with the method |
| PCT/EP2020/067042 WO2021001167A1 (de) | 2019-07-04 | 2020-06-18 | VERFAHREN ZUR LEITERPLATTENHERSTELLUNG SOWIE GEMÄß DEM VERFAHREN HERGESTELLTE LEITERPLATTEN |
| EP20734156.1A EP3994963A1 (de) | 2019-07-04 | 2020-06-18 | VERFAHREN ZUR LEITERPLATTENHERSTELLUNG SOWIE GEMÄß DEM VERFAHREN HERGESTELLTE LEITERPLATTEN |
| JP2021572092A JP2022537656A (ja) | 2019-07-04 | 2020-06-18 | 印刷回路板を製造するための方法、及びかかる方法に従って製造された印刷回路板 |
| CN202080048922.3A CN114009154A (zh) | 2019-07-04 | 2020-06-18 | 印刷电路板制造方法以及根据该方法制造的印刷电路板 |
| KR1020227003720A KR20220030279A (ko) | 2019-07-04 | 2020-06-18 | 인쇄회로기판 제조 방법 및 상기 제조 방법에 따라 제조된 인쇄회로기판 |
| TW109122330A TWI873155B (zh) | 2019-07-04 | 2020-07-02 | 製造印刷電路板的方法及依照該方法製造之印刷電路板 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102019209889.4A DE102019209889A1 (de) | 2019-07-04 | 2019-07-04 | Verfahren zur Leiterplattenherstellung sowie gemäß dem Verfahren hergestellte Leiterplatten |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102019209889A1 true DE102019209889A1 (de) | 2021-01-07 |
Family
ID=71120168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102019209889.4A Pending DE102019209889A1 (de) | 2019-07-04 | 2019-07-04 | Verfahren zur Leiterplattenherstellung sowie gemäß dem Verfahren hergestellte Leiterplatten |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20220361341A1 (https=) |
| EP (1) | EP3994963A1 (https=) |
| JP (1) | JP2022537656A (https=) |
| KR (1) | KR20220030279A (https=) |
| CN (1) | CN114009154A (https=) |
| DE (1) | DE102019209889A1 (https=) |
| TW (1) | TWI873155B (https=) |
| WO (1) | WO2021001167A1 (https=) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102021209939A1 (de) | 2021-09-08 | 2023-03-09 | Gebr. Schmid Gmbh | Verfahren zur Leiterplattenherstellung und Leiterplatte |
| WO2024260610A1 (de) * | 2023-06-23 | 2024-12-26 | Gebr. Schmid Gmbh | Verfahren zur leiterplattenherstellung |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115884494A (zh) * | 2021-09-28 | 2023-03-31 | 深南电路股份有限公司 | 一种线路内埋方法及线路内埋pcb板 |
| CN114725026A (zh) * | 2022-03-04 | 2022-07-08 | 苏州链芯半导体科技有限公司 | 一种叠加先进塑料的柔性无芯3d印刷集成电路模压工艺 |
| CN114745845B (zh) * | 2022-04-30 | 2023-08-08 | 苏州浪潮智能科技有限公司 | 一种印刷电路板及制造方法 |
| DE102024125859A1 (de) * | 2024-09-09 | 2026-03-12 | Gebr. Schmid Gmbh | Verfahren zur Herstellung mehrschichtiger Substrate mit einer integrierten Leiterstruktur und gemäss dem Verfahren herstellbare mehrschichtige Substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
| US5244538A (en) * | 1991-07-26 | 1993-09-14 | Microelectronics And Computer Technology Corporation | Method of patterning metal on a substrate using direct-write deposition of a mask |
| US20120291275A1 (en) * | 2011-05-19 | 2012-11-22 | Korea Institute Of Machinery & Materials | Method of forming metal interconnection line on flexible substrate |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3373256D1 (en) * | 1983-05-19 | 1987-10-01 | Ibm Deutschland | Process for manufacturing printed circuits with metallic conductor patterns embedded in the isolating substrate |
| JPH0724328B2 (ja) * | 1989-07-03 | 1995-03-15 | ポリプラスチックス株式会社 | 精密細線回路用成形品の製造方法 |
| JP3361556B2 (ja) * | 1992-09-25 | 2003-01-07 | 日本メクトロン株式会社 | 回路配線パタ−ンの形成法 |
| JPH07240568A (ja) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | 回路基板およびその製造方法 |
| JP3726500B2 (ja) * | 1997-07-28 | 2005-12-14 | 株式会社日立製作所 | 配線板及びその製造方法並びに無電解めっき方法 |
| US6518160B1 (en) * | 1998-02-05 | 2003-02-11 | Tessera, Inc. | Method of manufacturing connection components using a plasma patterned mask |
| US7091589B2 (en) * | 2002-12-11 | 2006-08-15 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and manufacture method thereof |
| JP2005332928A (ja) * | 2004-05-19 | 2005-12-02 | Sumitomo Heavy Ind Ltd | プリント配線板の製造方法 |
| US20060127686A1 (en) * | 2004-12-15 | 2006-06-15 | Meloni Paul A | Thermally conductive polyimide film composites having high thermal conductivity useful in an electronic device |
| TWI253714B (en) * | 2004-12-21 | 2006-04-21 | Phoenix Prec Technology Corp | Method for fabricating a multi-layer circuit board with fine pitch |
| KR101022914B1 (ko) * | 2008-11-04 | 2011-03-16 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
| JP5892157B2 (ja) * | 2011-03-25 | 2016-03-23 | 住友ベークライト株式会社 | プリント配線基板、プリント配線基板の製造方法および半導体装置 |
| CN102315163A (zh) * | 2011-09-28 | 2012-01-11 | 上海华力微电子有限公司 | 超低介电常数薄膜铜互连的制作方法 |
| US20140027163A1 (en) * | 2012-07-30 | 2014-01-30 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method for manufacturing the same |
| JP6044592B2 (ja) * | 2014-05-29 | 2016-12-14 | トヨタ自動車株式会社 | 多層配線基板及びその製造方法 |
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2019
- 2019-07-04 DE DE102019209889.4A patent/DE102019209889A1/de active Pending
-
2020
- 2020-06-18 US US17/624,082 patent/US20220361341A1/en active Pending
- 2020-06-18 CN CN202080048922.3A patent/CN114009154A/zh active Pending
- 2020-06-18 EP EP20734156.1A patent/EP3994963A1/de active Pending
- 2020-06-18 WO PCT/EP2020/067042 patent/WO2021001167A1/de not_active Ceased
- 2020-06-18 JP JP2021572092A patent/JP2022537656A/ja active Pending
- 2020-06-18 KR KR1020227003720A patent/KR20220030279A/ko active Pending
- 2020-07-02 TW TW109122330A patent/TWI873155B/zh active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
| US5244538A (en) * | 1991-07-26 | 1993-09-14 | Microelectronics And Computer Technology Corporation | Method of patterning metal on a substrate using direct-write deposition of a mask |
| US20120291275A1 (en) * | 2011-05-19 | 2012-11-22 | Korea Institute Of Machinery & Materials | Method of forming metal interconnection line on flexible substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102021209939A1 (de) | 2021-09-08 | 2023-03-09 | Gebr. Schmid Gmbh | Verfahren zur Leiterplattenherstellung und Leiterplatte |
| WO2024260610A1 (de) * | 2023-06-23 | 2024-12-26 | Gebr. Schmid Gmbh | Verfahren zur leiterplattenherstellung |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2022537656A (ja) | 2022-08-29 |
| KR20220030279A (ko) | 2022-03-10 |
| CN114009154A (zh) | 2022-02-01 |
| WO2021001167A1 (de) | 2021-01-07 |
| TW202109622A (zh) | 2021-03-01 |
| US20220361341A1 (en) | 2022-11-10 |
| EP3994963A1 (de) | 2022-05-11 |
| TWI873155B (zh) | 2025-02-21 |
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