DE102013106577B4 - Package-in-Packages und Verfahren zu ihrer Herstellung - Google Patents

Package-in-Packages und Verfahren zu ihrer Herstellung Download PDF

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DE102013106577B4
DE102013106577B4 DE102013106577.5A DE102013106577A DE102013106577B4 DE 102013106577 B4 DE102013106577 B4 DE 102013106577B4 DE 102013106577 A DE102013106577 A DE 102013106577A DE 102013106577 B4 DE102013106577 B4 DE 102013106577B4
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semiconductor
semiconductor chip
semiconductor module
leadframe
module
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DE102013106577A1 (de
Inventor
Ralf Otremba
Josef Hoeglauer
Jürgen Schredl
Xaver Schloegel
Klaus Schiess
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

Halbleitervorrichtung, umfassend:einen Leadframe (300), welcher mehrere Leads (320) und ein Die-Paddle (310) umfasst;ein Halbleiter-Modul (100), welches an einer Oberfläche des Die-Paddle (310) des Leadframe (300) angebracht ist, wobei das Halbleiter-Modul (100) einen ersten Halbleiter-Chip (20, 21, 25) und einen zweiten Halbleiter-Chip (20, 21,25) umfasst, welche in ein erstes Kapselungsmaterial (50) eingebettet sind, wobei die Halbleiter-Chips (20,21,25) derart lateral nebeneinander angeordnet sind, dass laterale Oberflächen der Halbleiter-Chips (20,21,25) welche senkrecht zur Oberfläche des Die-Paddle (310) angeordnet sind, einander gegenüberliegen, wobei das Halbleiter-Modul (100) mehrere mit dem ersten Halbleiter-Chip (20,21,25) gekoppelte Kontaktpads (90) umfasst;mehrere Verbindungen (330), welche die mehreren Kontaktpads (90) mit den mehreren Leads (320) koppeln; undein zweites Kapselungsmaterial (350), welches auf dem Halbleiter-Modul (100) und dem Leadframe (300) angeordnet ist, wobei der erste Halbleiter-Chip (20,21,25) und der zweite Halbleiter-Chip (20,21,25) durch eine an ihren Vorderseiten, in der Nähe einer ersten Seite des Halbleiter-Moduls (100) angeordnete Umverdrahtungsschicht gekoppelt sind, wobei die Vorderseiten von dem Die-Paddle (310) wegweisen, wobei die Umverdrahtungsschicht eine gemeinsame Passivierungsschicht (60) und gemeinsame Umverdrahtungsleitungen (150) der Halbleiter-Chips (20,21,25) aufweist, und wobei die Umverdrahtungsleitungen (150) von dem zweiten Kapselungsmaterial (350) bedeckt sind.

Description

  • Die vorliegende Erfindung bezieht sich im Allgemeinen auf Halbleiter-Bauelemente (oder Halbleitervorrichtungen) und insbesondere auf Package-in-Packages und Verfahren zu ihrer Herstellung.
  • Halbleiter-Bauelemente werden in einer Vielzahl von elektronischen und anderen Anwendungen eingesetzt. Halbleiter-Bauelemente umfassen, neben anderem, integrierte Schaltungen und diskrete Bauelemente, die auf Halbleiter-Wafern ausgebildet werden, indem mehrere Arten von Material-Dünnschichten auf den Halbleiter-Wafern abgeschieden werden, und indem die Material-Dünnschichten zum Ausbilden integrierter Schaltungen strukturiert werden.
  • Die Halbleiter-Bauelemente sich typischerweise in einem Keramik- oder Plastikkörper gehäust (engl. packaged), um die Halbleiter-Bauelemente vor physischer Beschädigung oder Korrosion zu schützen. Das Packaging (oder Package) stützt außerdem die elektrischen Kontakte, die erforderlich sind, um ein Halbleiter-Bauelement, auch Die oder Chip genannt, mit anderen Bauelementen außerhalb des Packaging zu verbinden. Viele unterschiedliche Packaging-Typen sind je nach Typ des Halbleiter-Bauelements und beabsichtigter Verwendung des Halbleiter-Bauelements, das gehäust wird, erhältlich. Typische Packaging-Merkmale, wie zum Beispiel die Maße des Packages, Anzahl der Pins usw., erfüllen möglicherweise unter anderem die offenen Standards des Joint Electron Devices Engineering Council (JEDEC). Packaging kann auch als Halbleiter-Bauelemente-Zusammenbau oder einfach Zusammenbau bezeichnet werden.
  • Obwohl die Größe von Halbleiter-Chips kontinuierlich sinkt, was auf die Größenreduzierungen in der Halbleiter-Technologie zurückzuführen ist, verkleinert sich daher, aufgrund der Notwendigkeit, standardisierte Packaging-Abmaße einzuhalten, die Größe der Packages nicht. Weiterhin enthält in zunehmend vielen Anwendungen ein einzelnes Package möglicherweise mehrere Halbleiter-Dies oder -Chips. Jedoch können konventionelle Packages nicht mehrere Halbleiter-Chips bzw. sehr kleine Halbleiter-Chips stützen. Die US 6 906 416 B2 offenbart eine Halbleitervorrichtung mit einem auf einem Substrat angeordneten Halbleiter-Modul, wobei das Halbleiter-Modul einen ersten und einen zweiten Halbleiter-Chip aufweist, welche in ein erstes Kapselungsmaterial eingebettet sind. Ein zweites Kapselungsmaterial der Halbleitervorrichtung ist auf dem Halbleiter-Modul und dem Substrat angeordnet. Weitere Halbleitervorrichtungen sind in der US 2003 / 0 032 216 A1 , der US 2012 / 0 126 429 A1 und der US 7 969 018 B2 offenbart.
  • Im Allgemeinen werden durch die veranschaulichenden Ausführungsformen der vorliegenden Erfindung diese und andere Probleme gelöst oder umgangen, und im Allgemeinen werden technische Vorteile erreicht.
  • Die Erfindung wird in durch die Merkmale der nebengeordneten Ansprüche beschrieben. Weitere vorteilhafte Ausführungsformen werden durch die Merkmale der abhängigen Ansprüche beschrieben.
  • Gemäß einem Beispiel umfasst ein Halbleiter-Bauelement einen Leadframe, der mehrere Leads und ein Die-Paddle (oder Diepad) aufweist, sowie ein Halbleiter-Modul, das am Die-Paddle des Leadframe angebracht ist. Das Halbleiter-Modul umfasst einen ersten Halbleiter-Chip, der in einem ersten Kapselungsmaterial angeordnet ist. Das Halbleiter-Modul weist mehrere Kontaktpads auf, die mit dem ersten Halbleiter-Chip verbunden sind. Das Halbleiter-Bauelement umfasst weiterhin mehrere Verbindungen, die die mehreren Kontaktpads mit den mehreren Leads verbinden, und ein zweites Kapselungsmaterial, das auf dem Halbleiter-Modul und dem Leadframe angeordnet ist.
  • Gemäß einem Beispiel umfasst ein Halbleiter-Bauelement einen Leadframe, der mehrere Leads und ein Die-Paddle aufweist, sowie ein Halbleiter-Modul, das über dem Die-Paddle des Leadframe angebracht ist. Das Halbleiter-Modul umfasst einen ersten Halbleiter-Chip und weist mehrere Kontaktpads auf, die mit dem ersten Halbleiter-Chip verbunden sind. Das Halbleiter-Modul ist ein Embedded Wafer Level Package. Ein Kapselungsmaterial ist auf dem Halbleiter-Modul und dem Leadframe angeordnet.
  • Gemäß einem Beispiel umfasst ein Halbleiter-Bauelement ein Halbleiter-Package, das innerhalb eines Leadframe-Packages angeordnet ist. Das Halbleiter-Package ist ein nicht standardisiertes Package, wohingegen das Leadframe-Package ein standardisiertes Package ist, das einen Standard erfüllt. Das Halbleiter-Package und das Leadframe-Package weisen im Wesentlichen die gleiche Funktionalität auf.
  • Gemäß einem Beispiel umfasst ein Verfahren zum Ausbilden eines Halbleiter-Bauelements das Bereitstellen eines Leadframe, der mehrere Leads und ein Die-Paddle aufweist. Ein Halbleiter-Modul wird bereitgestellt, das einen ersten, in einem ersten Kapselungsmaterial angeordneten Halbleiter-Chip umfasst. Das Halbleiter-Modul weist mehrere, mit dem ersten Halbleiter-Chip verbundene Kontaktpads auf. Das Halbleiter-Modul ist am Die-Paddle des Leadframe angebracht. Die mehreren Kontaktpads sind elektrisch mit den mehreren Leads verbunden. Das Halbleiter-Modul und der Leadframe sind mit einem zweiten Kapselungsmaterial gekapselt.
  • Für ein vollständigeres Verständnis der vorliegenden Erfindung und ihrer Vorteile wird jetzt Bezug auf die folgenden Beschreibungen in Verbindung mit den zugehörigen Zeichnungen genommen, dabei veranschaulichen:
    • 1, die die 1A und 1B enthält, ein Halbleiter-Package gemäß einem nicht erfindungsgemäßen Beispiel, wobei 1A eine Draufsicht veranschaulicht und 1B eine Querschnittsansicht veranschaulicht;
    • 2, die die 2A - 2B enthält, eine Ausführungsform des Halbleiter-Packages, und die frontseitigen Umverdrahtungsleitungen, wobei 2A eine Draufsicht veranschaulicht und wobei 2B eine Querschnittsansicht veranschaulicht;
    • 3, die die 3A - 3E enthält, weitere bauliche Ausführungsformen des Halbleiter-Packages, wobei 3A den Leadframe und das Halbleiter-Modul des Halbleiter-Packages veranschaulicht und wobei die 3B - 3E Beispiele für das Halbleiter-Modul veranschaulichen;
    • die 4 - 15 eine Querschnittsansicht eines Halbleiter-Packages in verschiedenen Stufen der Herstellung gemäß einer Ausführungsform der vorliegenden Erfindung;
    • die 16 - 17 eine Querschnittsansicht eines Halbleiter-Packages in verschiedenen Herstellungsstufen gemäß einer alternativen Ausführungsform der vorliegenden Erfindung; und
    • 18 ein anderes nicht erfindungsgemäßes Beispiel des Halbleiter-Packages, das ein gestapeltes Halbleiter-Package-in-Package veranschaulicht.
  • Entsprechende Nummerierungen und Symbole in den verschiedenen Figuren beziehen sich im Allgemeinen auf entsprechende Teile, es sei denn, es ist anders angegeben. Die Figuren sind gezeichnet, um die maßgeblichen Aspekte der Ausführungsformen klar zu veranschaulichen, und sind nicht notwendigerweise maßstabsgetreu gezeichnet.
  • Die Herstellung und die Verwendung von verschiedenen Ausführungsformen werden unten ausführlich erörtert. Es versteht sich jedoch, dass die vorliegende Erfindung viele anwendbare, erfindungsgemäße Konzepte bereitstellt, welche in sehr vielen verschiedenen, spezifischen Zusammenhängen umgesetzt werden können. Die erörterten spezifischen Ausführungsformen dienen lediglich der Veranschaulichung spezifischer Wege, die Erfindung herzustellen und zu verwenden, und schränken nicht das Konzept der Erfindung ein.
  • Ausführungsformen der Erfindung ermöglichen das Ausbilden von Packages mit standardisierten Abmaßen, zum Beispiel von Packages, die den JEDEC-Standards entsprechen, die jedoch auch die Integration mehrerer Halbleiter-Chips innerhalb des Packages ohne Anstieg der Packaging-Kosten ermöglichen.
  • Ein nicht erfindungsgemäßes Beispiel wird unter Verwendung von 1 beschrieben. Strukturelle Ausführungsformen der vorliegenden Erfindung werden unter Verwendung der 2, 3 und 18 beschrieben. Verfahren zum Ausbilden des Halbleiter-Packages werden unter Verwendung der 4 - 15 und der 16 - 17 gemäß Ausführungsformen der vorliegenden Erfindung beschrieben.
  • 1, die die 1A und 1B enthält, zeigt ein Halbleiter-Package gemäß einem nicht erfindungsgemäßen Beispiel, wobei 1A eine Draufsicht veranschaulicht und 1B eine Querschnittsansicht veranschaulicht.
  • Gemäß 1A umfasst das Halbleiter-Package einen Leadframe 300, der ein Die-Paddle (oder Diepad) 310 und mehrere Leads 320 aufweist. Ein Halbleiter-Modul 100 ist am Die-Paddle 310 des Leadframe 300 angebracht. In verschiedenen Ausführungsformen umfasst das Halbleiter-Modul 100 möglicherweise mehrere Halbleiter-Chips 20.
  • In verschiedenen Beispielen können die mehreren Halbleiter-Chips 20 unterschiedliche Die-Typen umfassen, einschließlich integrierter Schaltungen oder diskreter Bauelemente. In einem oder mehreren Beispielen umfasst jeder der mehreren Halbleiter-Chips 20 möglicherweise Logikchips, Speicherchips, Analogchips, Mixed-Signal Chips und Kombinationen aus diesen, wie zum Beispiel ein System on Chip. Die mehreren Halbleiter-Chips 20 können verschiedene Typen aktiver und passiver Bauelemente umfassen, wie zum Beispiel Dioden, Transistoren, Thyristoren, Kondensatoren, Induktivitäten, Widerstände, optoelektronische Bauelemente, Sensoren, mikro-elektromechanische Systeme und andere. Die mehreren Halbleiter-Chips 20 können ähnliche Halbleiter-Chip-Typen oder verschiedene Halbleiter-Chip-Typen in verschiedenen Ausführungsformen sein.
  • In verschiedenen Beispielen können die mehreren Halbleiter-Chips 20 auf einem Silizium-Substrat ausgebildet werden. Alternativ können in anderen Beispielen die mehreren Halbleiter-Chips 20 auf Siliziumkarbid (SiC) ausgebildet worden sein. In einem Beispiel können die mehreren Halbleiter-Chips 20 wenigstens zum Teil auf Galliumnitrid (GaN) ausgebildet worden sein.
  • In verschiedenen Beispielen umfassen die mehreren Halbleiter-Chips 20 möglicherweise ein Leistungshalbleiter-Bauelement, das in einem Beispiel ein diskretes Bauelement sein kann. In einem Beispiel sind wenigstens einige der mehreren Halbleiter-Chips 20 Bauelemente mit zwei Anschlusspunkten (engl. two terminal device), wie zum Beispiel PIN-Dioden oder Schottky-Dioden. In einem oder mehreren Beispielen sind wenigstens einige der mehreren Halbleiter-Chips 20 Bauelemente mit drei Anschlusspunkten (engl. three terminal device), wie zum Beispiel ein Leistungs-Metall-Isolator-Halbleiter-Feldeffekt-Transistor (MISFET, metal insulator semiconductor field effect transistor), ein Junction Field Effect Transistor (JFET), bipolarer Sperrschichttransistor (BJT, bipolar junction transistor), ein Bipolartransistor mit isolierter Steuerelektrode (IGBT, insulated gate bipolar transistor) oder ein Thyristor.
  • Das Halbleiter-Modul 100 umfasst in einigen Beispielen mehrere Kontaktpads 90 zur Montage des Halbleiter-Moduls 100 über einer Platine (engl. circuit board). Zur Veranschaulichung: Die mehreren Kontaktpads 90 enthalten ein erstes Kontaktpad 110, ein zweites Kontaktpad 120 und ein drittes Kontaktpad 130, welche die Kontakte für einen der mehreren Halbleiter-Chips 20 ausbilden. Das dritte Kontaktpad 130 der mehreren Kontaktpads 90 wird möglicherweise mit einer Rückseite der mehreren Halbleiter-Chips 20 verbunden. Zum Beispiel ist in einem oder in mehreren Beispielen das dritte Kontaktpad 130 möglicherweise unter Verwendung von vertikalen Substrat-Durchkontaktierungen (engl. substrate vias) 260 verbunden, die in dem Kapselungsmaterial 50 angeordnet sind. Ähnlich enthält der andere Chip der mehreren Halbleiter-Chips 20 ein erstes Kontaktpad 110, ein zweites Kontaktpad 120 und ein drittes Kontaktpad 130.
  • Die mehreren Halbleiter-Chips 20 werden in verschiedenen Beispielen möglicherweise mit den mehreren Leads 320 unter Verwendung von Drahtbonds (oder Drahtverbindungen) 330 verbunden. In alternativen Beispielen werden die mehreren Halbleiter-Chips 20 möglicherweise unter Verwendung anderer Verbindungen verbunden, wie zum Beispiel mit Clips, Leads, Streifen oder auf anderen, zum Verbinden geeigneten Wegen.
  • Wie in 1A veranschaulicht wird, sind die mehreren Halbleiter-Chips 20 innerhalb des Halbleiter-Moduls 100 in ein Kapselungsmaterial 50 eingebettet. Das Halbleiter-Modul 100 selbst ist in ein äußeres Kapselungsmaterial 350 eingebettet.
  • Gemäß 1B ist das Halbleiter-Modul 100 am Die-Paddle 310 des Leadframe 300 unter Verwendung einer Die-Attach-Schicht 280 angebracht. Die Die-Attach-Schicht 280 kann in unterschiedlichen Beispielen eine isolierende Schicht oder eine leitfähige Schicht sein.
  • Wie in der Querschnittsansicht in 1B veranschaulicht wird, sind die mehreren Halbleiter-Chips 20 im Kapselungsmaterial 50 eingebettet. Ein erstes Kontaktpad 110 ist über den mehreren Halbleiter-Chips 20 angeordnet. Ein rückseitiges Füllmaterial 250 ist mit den rückseitigen Kontaktbereichen der mehreren Halbleiter-Chips 20 verbunden. Das rückseitige Füllmaterial 250 ist mit der Frontseite des Halbleiter-Moduls 100 unter Verwendung von vertikalen Substrat-Durchkontaktierungen (oder Substrat-Vias) 260 verbunden, die in das Kapselungsmaterial 50 eingebettet sind. Benachbarte Chips der mehreren Halbleiter-Chips 20 sind voneinander durch das isolierende Kapselungsmaterial 50 isoliert. Die mehreren Kontaktpads 90, die das erste Kontaktpad 110 und das dritte Kontaktpad 130 enthalten, sind mit den mehreren Leads 320 unter Verwendung von Drahtbonds 330 verbunden. Die Drahtbonds 330 können unter Verwendung von ball- oder keil(wedge)-förmigen Lotkugeln 340 gebondet sein.
  • In verschiedenen Beispielen kann das Halbleiter-Modul 100 ein Package sein, welches nicht konform zu standardisierten Packaging-Modulen ist, wie zum Beispiel gemäß den JEDEC-Standards. Jedoch ist in verschiedenen Ausführungsformen das ausgebildete Leadframe-Package konform zu standardisiertem Packaging, wie zum Beispiel gemäß den JEDEC-Standards. Jedoch weisen sowohl das Halbleiter-Modul 100 als auch das Leadframe-Package ähnliche Funktion und Wirkungsweise auf, zum Beispiel weist das Leadframe-Package möglicherweise keine zusätzlichen Halbleiter-Bauelemente neben denen im Halbleiter-Modul 100 auf.
  • 2, die die 2A - 2B enthält, veranschaulicht eine Ausführungsform des Halbleiter-Packages, die die frontseitigen Umverdrahtungsleitungen veranschaulicht, wobei 2A eine Draufsicht veranschaulicht und wobei 2B eine Querschnittsansicht veranschaulicht.
  • Zusätzlich zu der in Bezug auf 1 beschriebenen Beispielen werden die mehreren Halbleiter-Chips 20 möglicherweise innerhalb des Halbleiter-Moduls 100 durchverbunden, zum Beispiel unter Verwendung von frontseitigen Umverdrahtungsleitungen 150. Somit kann sich die Anzahl der Pads der mehreren Kontaktpads 90 auf dem Halbleiter-Modul 100 von der Anzahl der Pins oder der mehreren Leads 320 des Leadframe 300 unterscheiden. Zum Beispiel, zur Veranschaulichung, weist das Halbleiter-Modul 100 sechs Kontaktpads auf, wohingegen der Leadframe 300 nur fünf Leads aufweist.
  • 3, die die 3A - 3E enthält, veranschaulicht weitere bauliche Ausführungsformen des Halbleiter-Packages, wobei 3A den Leadframe und das Halbleiter-Modul des Halbleiter-Packages veranschaulicht und wobei die 3B - 3E Beispiele für das Halbleiter-Modul veranschaulichen.
  • 3A veranschaulicht den Leadframe 300, der mehrere Leads 320 und ein Die-Paddle 310 aufweist. Der Leadframe 300 enthält auch die mehreren Pins 305, die sich von den mehreren Leads 320 her ausdehnen. Das Halbleiter-Modul 100 ist über dem Die-Paddle 310 angeordnet.
  • Gemäß 3B enthält das Halbleiter-Modul 100 möglicherweise mehrere Kontaktpads 90, die von den funktionalen Chips 25, wie zum Beispiel Logik-, Analog- oder Speicherchips, durch die frontseitigen Umverdrahtungsleitungen 150 getrennt sind. Wie veranschaulicht, können die mehreren Halbleiter-Chips 20 unter Verwendung der frontseitigen Umverdrahtungsleitungen 150 verbunden sein, die möglicherweise auch verwendet werden, um die mehreren Kontaktpads 90 zu verbinden.
  • 3C veranschaulicht eine alternative Ausführungsform die ein Leistungsbauelement umfasst, wie zum Beispiel einen diskreten Hochspannungstransistor. Wie veranschaulicht, enthalten die mehreren Kontaktpads 90 ein erstes Kontaktpad 110, ein zweites Kontaktpad 120, ein drittes Kontaktpad 130, das mit einem rückseitigen Leiter, z.B. einem leitfähigen Füllmaterial 250, verbunden ist, und ein viertes Kontaktpad 140.
  • 3D veranschaulicht eine andere alternative Ausführungsform die eine integrierte Niedrigspannungsschaltung umfasst. 3E, die die 3E-1 und 3E-2 enthält, veranschaulicht eine weitere Ausführungsform die mehrere Halbleiter-Chips umfasst, die unter Verwendung von frontseitigen Umverdrahtungsleitungen verbunden worden sind. In 3E-1 wird das Kontaktpad 90 unter Verwendung von Phantom-Linien gezeigt, um die Merkmale unterhalb des Kontaktpads 90 herauszustellen. 3E-2 veranschaulicht das Kontaktpad 90 als massives Material, so dass die Merkmale unterhalb mit gestrichelten Linien dargestellt werden.
  • Die 4 - 15 veranschaulichen ein Verfahren zur Herstellung des Halbleiter-Packages gemäß einer Ausführungsform der vorliegenden Erfindung.
  • 4 veranschaulicht ein Halbleiter-Package während der Herstellung, nachdem vereinzelte Dies über einem Träger platziert wurden, gemäß einer Ausführungsform der Erfindung.
  • Gemäß 4 werden mehrere Halbleiter-Chips 20 über einem Träger 10 platziert. In verschiedenen Ausführungsformen wird die erste Oberfläche 11 der mehreren, aktive Bereiche aufweisenden Halbleiter-Chips 20 auf den Träger 10 gerichtet platziert, wie in 4 veranschaulicht wird.
  • Die mehreren Halbleiter-Chips 20 werden möglicherweise unter Verwendung von konventioneller Verarbeitung ausgebildet, zum Beispiel innerhalb eines Wafers, der zum Ausbilden der mehreren Halbleiter-Chips 20 vereinzelt (diced) wird. Wie oben beschrieben werden die mehreren Halbleiter-Chips 20 möglicherweise auf einem Silizium-Substrat ausgebildet, wie zum Beispiel einem Bulk-Silizium-Substrat oder einem Silizium-auf-Isolator-Substrat (SOI). Alternativ kann der Halbleiter-Chip 20 ein auf Siliziumkarbid (SiC) ausgebildetes Bauelement sein. Ausführungsformen der Erfindung können möglicherweise auch Bauelemente enthalten, die auf Verbundhalbleitersubstraten ausgebildet werden, und enthalten möglicherweise Bauelemente auf hetero-epitaxialen Substraten. In einer Ausführungsform ist der Halbleiter-Chip 20 ein Bauelement, das wenigstens zum Teil auf Galliumnitrid (GaN) ausgebildet wird, welches ein GaN auf Saphir- (GaN on sapphire) oder Silizium-Substrat sein kann.
  • In verschiedenen Ausführungsformen umfassen die mehreren Halbleiter-Chips 20 möglicherweise Leistungs-Chips, die zum Beispiel große Ströme ziehen (z.B. größer als 30 Ampere). In verschiedenen Ausführungsformen umfassen die mehreren Halbleiter-Chips 20 möglicherweise diskrete vertikale Bauelemente, wie zum Beispiel ein Leistungsbauelement mit zwei oder drei Anschlusspunkten. Beispiele für die mehreren Halbleiter-Chips 20 sind u.a. PIN- oder Schottky-Dioden, MISFET, JFET, BJT, IGBT oder Thyristor. In verschiedenen Ausführungsformen umfassen die mehreren Halbleiter-Chips 20 möglicherweise eine Kombination aus Leistungs-Chips 21 und funktionalen Chips 25, wie zum Beispiel Logik- oder Speicherchips.
  • In verschiedenen Ausführungsformen können die Leistungs-Chips 21 ein vertikales Halbleiter-Bauelement sein, das zum Betrieb bei etwa 20 V bis etwa 1000 V konfiguriert ist. In einer Ausführungsform sind die Leistungs-Chips 21 zum Betrieb bei etwa 20 V bis etwa 100 V konfiguriert. In einer anderen Ausführungsform sind die Leistungs-Chips 21 zum Betrieb bei etwa 100 V bis etwa 500 V konfiguriert. In noch einer anderen Ausführungsform sind die Leistungs-Chips 21 zum Betrieb bei etwa 500 V bis etwa 1000 V konfiguriert. In einer Ausführungsform sind die Leistungs-Chips 21 ein npn-Transistor. In einer anderen Ausführungsform sind die Leistungs-Chips 21 ein pnp-Transistor. In noch einer anderen Ausführungsform sind die Leistungs-Chips 21 ein n-Kanal MISFET. In einer weiteren Ausführungsform sind die Leistungs-Chips 21 ein p-Kanal MISFET. In einer oder mehreren Ausführungsformen umfassen die Leistungs-Chips 21 möglicherweise mehrere Bauelemente, wie zum Beispiel einen vertikalen MISFET und eine Diode oder alternativ zwei durch einen Isolierbereich getrennte MISFET-Bauelemente.
  • Die Dicke der mehreren Halbleiter-Chips 20 von der oberen Oberfläche 11 zur unteren Oberfläche 12 kann in verschiedenen Ausführungsformen weniger als 50 µm (Mikrometer) betragen. Die Dicke der mehreren Halbleiter-Chips 20 von der oberen Oberfläche 11 zur unteren Oberfläche 12 kann in einer oder mehreren Ausführungsformen weniger als 20 µm (Mikrometer) betragen. Die Dicke der mehreren Halbleiter-Chips 20 von der oberen Oberfläche 11 zur unteren Oberfläche 12 kann in einer oder mehreren Ausführungsformen weniger als 10 µm (Mikrometer) betragen.
  • Als Nächstes werden die mehreren Halbleiter-Chips 20 am Träger 10 angebracht, der mechanische Stützung und Stabilität während der Verarbeitung bereitstellt. In verschiedenen Ausführungsformen kann der Träger 10 eine Platte aus einem starren Material sein, zum Beispiel ein Metall, wie zum Beispiel Nickel, Stahl oder Edelstahl, ein Laminat, ein Film oder ein Materialstapel. Der Träger 10 weist möglicherweise wenigstens eine flache Oberfläche auf, über der möglicherweise die mehreren Halbleiter-Chips 20 platziert werden. In einer oder mehreren Ausführungsformen kann der Träger 10 rund oder quadratisch sein, obwohl der Träger 10 in verschiedenen Ausführungsformen jede geeignete Gestalt aufweisen kann. Der Träger 10 kann in verschiedenen Ausführungsformen jede geeignete Größe aufweisen. In einigen Ausführungsformen enthält der Träger 10 möglicherweise ein Klebeband, zum Beispiel ein doppelseitiges klebendes Band, das auf den Träger 10 laminiert wird. Der Träger 10 kann einen Rahmen umfassen, der eine Ringstruktur aufweist (ringförmig ist), mit einer Klebefolie in einer Ausführungsform. Die Klebefolie wird in einer oder mehreren Ausführungsformen möglicherweise längs der äußeren Kanten vom Rahmen gestützt.
  • Die mehreren Halbleiter-Chips 20 werden in verschiedenen Ausführungsformen möglicherweise unter Verwendung einer Klebeschicht 35 angebracht. In verschiedenen Ausführungsformen umfasst die Klebeschicht 35 möglicherweise einen Klebstoff oder anderes kleberartiges Material. In verschiedenen Ausführungsformen ist die Klebeschicht 35 möglicherweise dünn, zum Beispiel weniger als etwa 100 µm (Mikrometer) in einer Ausführungsform und zwischen 1 µm (Mikrometer) und 50 µm (Mikrometer) in einer anderen Ausführungsform.
  • 5 veranschaulicht das Halbleiter-Package während der Herstellung, nachdem, gemäß einer Ausführungsform der Erfindung, ein rekonstituierter Wafer ausgebildet worden ist.
  • Wie in 5 veranschaulicht wird, wird ein Kapselungsmaterial 50 über den mehreren Halbleiter-Chips 20 aufgebracht und kapselt zum Teil die mehreren Halbleiter-Chips 20. In einer Ausführungsform wird das Kapselungsmaterial 50 unter Verwendung eines Formgieß-Prozesses (molding) aufgebracht, wie zum Beispiel Formpressen (compression molding), ein Transferpress-Prozess (transfer molding), Spritzguss, Granulatspritzguss (granulate molding), Pulverschmelzverfahren (powder molding), Gießen, oder auch von Druck-Prozessen, wie zum Beispiel Schablonendruck oder Siebdruck.
  • In verschiedenen Ausführungsformen umfasst das Kapselungsmaterial 50 ein dielektrisches Material und umfasst in einer Ausführungsform möglicherweise eine Gussmasse (engl. mold compound). In anderen Ausführungsformen umfasst das Kapselungsmaterial 50 möglicherweise ein oder mehrere Materialien von folgenden: einem Polymer, einem Copolymer, einem Biopolymer, einem faserimprägnierten Polymer (z.B. Kohle- oder Glasfasern in einem Harz), einem partikelgefüllten Polymer oder anderen organischen Materialien. In einer oder mehreren Ausführungsformen umfasst das Kapselungsmaterial 50 ein Dichtungsmittel, das nicht unter Verwendung einer Gussmasse ausgebildet wird, und Materialien wie zum Beispiel Epoxidharze und/oder Silikone. In verschiedenen Ausführungsformen wird das Kapselungsmaterial 50 möglicherweise aus jedem geeigneten Duroplast, Thermoplast, einem wärmeaushärtendem Material oder einem Laminat hergestellt. Das Material des Kapselungsmaterials 50 enthält in einigen Ausführungsformen möglicherweise Füllmaterialien. In einer Ausführungsform umfasst das Kapselungsmaterial 50 möglicherweise Epoxidharzmaterial und ein Füllmaterial, das kleine Glaspartikel oder andere elektrisch isolierende mineralische Füllmaterialien, wie Aluminiumoxid oder organische Füllmaterialien, umfasst. Das Kapselungsmaterial 50 wird möglicherweise gehärtet, z.B. einem thermischen Prozess unterworfen, um es auszuhärten und so eine hermetische Dichtung auszubilden, welche die mehreren Halbleiter-Chips 20 schützt. Der Härtungsprozess härtet das Kapselungsmaterial 50 aus, wodurch ein einzelnes Substrat ausgebildet wird, das die mehreren Halbleiter-Chips 20 hält. Solch ein Substrat wird als ein rekonstituierter Wafer 5 bezeichnet.
  • 6 veranschaulicht das Halbleiter-Package während der Herstellung, nachdem, gemäß einer Ausführungsform der Erfindung, der rekonstituierte Wafer vom Träger getrennt worden ist.
  • Gemäß 6 wird der Träger 10 entfernt, um den rekonstituierten Wafer 5 oder künstlichen Wafer abzutrennen. Das Kapselungsmaterial 50 stellt mechanische und thermische Stabilität während der folgenden Verarbeitung bereit. Durch Entfernen des Trägers 10 wird auch die frontseitige Oberfläche des Halbleiter-Chips 20 freigelegt. Während der folgenden Verarbeitung wird der rekonstituierte Wafer 5 möglicherweise Temperaturen von bis zu 300°C unterworfen, in Abhängigkeit von der thermischen Stabilität des Kapselungsmaterials 50 in verschiedenen Ausführungsformen.
  • 7 veranschaulicht eine vergrößerte Querschnittsansicht des Halbleiter-Packages während der Herstellung und zeigt die frontseitige Metallisierung gemäß einer Ausführungsform der Erfindung. Anders als die 4 - 6 veranschaulicht 7 eine vergrößerte Ansicht eines einzelnen Halbleiter-Packages.
  • Gemäß 7 enthalten die mehreren Halbleiter-Chips 20 möglicherweise eine frontseitige Metallisierungsschicht 15, zum Beispiel umfassen sie möglicherweise einen ersten Kontaktbereich 30 und einen zweiten Kontaktbereich 40. Die frontseitige Metallisierungsschicht 15 wird über der oberen Oberfläche 11 der mehreren Halbleiter-Chips 20 ausgebildet. In verschiedenen Ausführungsformen wird die frontseitige Metallisierungsschicht 15 möglicherweise ausgebildet, bevor der Wafer vereinzelt wird. Alternativ wird in einigen Ausführungsformen die frontseitige Metallisierungsschicht 15 möglicherweise während dieser Verarbeitungsstufe ausgebildet. Der erste Kontaktbereich 30 und der zweite Kontaktbereich 40 umfassen möglicherweise mehrere Schichten. In einer Ausführungsform decken Silizid-Bereiche möglicherweise ein Halbleitermaterial der mehreren Halbleiter-Chips 20 ab. Möglicherweise wird eine Sperrschicht über den Silizid-Bereichen ausgebildet, gefolgt von einer Metallschicht.
  • In einer Ausführungsform umfassen der erste Kontaktbereich 30 und der zweite Kontaktbereich 40 möglicherweise Kupfer. In einer anderen Ausführungsform umfassen der erste Kontaktbereich 30 und der zweite Kontaktbereich 40 möglicherweise Aluminium. In verschiedenen Ausführungsformen umfassen der erste Kontaktbereich 30 und der zweite Kontaktbereich 40 möglicherweise Titan, Tantal, Wolfram bzw. Nitride von diesen Elementen.
  • 8 veranschaulicht eine vergrößerte Ansicht des Halbleiter-Packages während des Ausbildens der frontseitigen Umverdrahtungsschicht gemäß einer Ausführungsform der Erfindung.
  • Eine Passivierungsschicht 60 wird möglicherweise um die frontseitige Metallisierungsschicht 15 ausgebildet und strukturiert, wodurch Umverdrahtungsleitungen und Kontaktpads ausgebildet werden. In verschiedenen Ausführungsformen ist die Passivierungsschicht 60 eine Isolierschicht. In einer oder mehreren Ausführungsformen umfasst die Passivierungsschicht 60 möglicherweise eine Oxid-Schicht oder einen Oxid/Nitrid-Schichtstapel. In anderen Ausführungsformen umfasst die Passivierungsschicht 60 möglicherweise Siliziumnitrid, Siliziumoxinitrid, FTEOS, SiCOH, Polyimid, Fotoimid, BCB (Benzocyclobutan) oder andere organische Polymere oder Kombinationen daraus. Ein optionaler Isolierbelag wird möglicherweise über der Passivierungsschicht 60 ausgebildet. Der optionale Isolierbelag umfasst in einer Ausführungsform möglicherweise eine Nitrid-Schicht. In verschiedenen Ausführungsformen umfasst der optionale Isolierbelag möglicherweise FTEOS, SiO2, SiCOH oder andere Low-k-Materialien. Unter Verwendung eines fotolithografischen Prozesses wird die Passivierungsschicht 60 strukturiert, um die Bondpads auf dem letzten Metallniveau der mehreren Halbleiter-Chips 20 freizulegen.
  • 9 veranschaulicht eine vergrößerte Ansicht des Halbleiter-Packages während der Herstellung, nach dem Ausbilden der frontseitigen Umverdrahtungsschicht gemäß einer Ausführungsform der Erfindung.
  • Gemäß 9 wird ein leitfähiger Belag 70 abgeschieden. In verschiedenen Ausführungsformen wird der leitfähige Belag 70 unter Verwendung eines Depositionsprozesses (Abscheidungsprozesses) abgeschieden, um eine Schutzschicht auszubilden, die Ti, Ta, Ru, W, Kombinationen daraus oder ein Nitrid, Silicid, Carbid von diesen Elementen umfasst. Beispiele für solche Kombinationen sind u.a. TiN, TaN und WN und TiW. In verschiedenen Ausführungsformen wird der leitfähige Belag 70 unter Verwendung einer chemischen Gasphasenabscheidung (chemical vapor deposition), einer plasmaunterstützten chemischen Gasphasenabscheidung (plasma vapor deposition) oder einer Atomlagenabscheidung (atomic layer deposition) abgeschieden. In verschiedenen Ausführungsformen umfasst der leitfähige Belag 70 eine Schichtstärke von etwa 20 nm bis etwa 200 nm. Der leitfähige Belag 70 ist ein Diffusionssperrmetall und verhindert sowohl das Ausdiffundieren von Kupfer aus der letzten Metallleitung der frontseitigen Metallisierungsschicht 15 als auch die Durchmischung mit weiteren Metallschichten.
  • Wie in 9 ferner veranschaulicht, wird eine leitfähige Keimschicht 80 abgeschieden. Die leitfähige Keimschicht 80 bedeckt den leitfähigen Belag 70. In verschiedenen Ausführungsformen wird die leitfähige Keimschicht 80 unter Verwendung eines Abscheidungsprozesses abgeschieden, um eine konforme Schicht auszubilden. In verschiedenen Ausführungsformen wird die leitfähige Keimschicht 80 unter Verwendung einer chemischen Gasphasenabscheidung, einer plasmaunterstützten chemischen Gasphasenabscheidung oder einer Atomlagenabscheidung abgeschieden. In verschiedenen Ausführungsformen umfasst die leitfähige Keimschicht 80 eine Schichtstärke von etwa 20 nm bis etwa 200 nm. Die leitfähige Keimschicht 80 stellt eine Keimschicht für das Wachstum während des nachfolgenden galvanischen Beschichtungsprozesses bereit. In verschiedenen Ausführungsformen umfasst die leitfähige Keimschicht 80 möglicherweise Kupfer oder andere Metalle wie Al, W, Ag, Au, Ni oder Pd.
  • Wie als Nächstes in 10 veranschaulicht wird, wird eine starke Fotoresistschicht 85 abgeschieden. In verschiedenen Ausführungsformen ist die Fotoresistschicht 85 einige Mikrometer stark und variiert in einer Ausführungsform von etwa 1 µm (Mikrometer) bis etwa 10 µm (Mikrometer). Nach der Deposition füllt die Fotoresistschicht 85 die Öffnungen, die vorher in der Passivierungsschicht 60 ausgebildet worden sind. Die Fotoresistschicht 85 liegt frei und ist entwickelt. Die strukturierte Fotoresistschicht 85 umfasst Strukturen für Umverdrahtungsmetallleitungen und Kontaktpads.
  • Gemäß 11 werden als Nächstes frontseitige Umverdrahtungsmetallleitungen 150 und Kontaktpads 90 durch galvanisches Beschichten mit einem Füllmetall über die leitfähige Keimschicht 80 ausgebildet, die zwischen der strukturierten Fotoresistschicht 85 frei liegt. In verschiedenen Ausführungsformen umfasst das Füllmetall Kupfer, wohingegen in einigen Ausführungsformen andere geeignete Leiter verwendet werden. Die leitfähige Keimschicht 80 kann das gleiche Material umfassen wie das Material der folgenden Metallleitungen, um in einer Ausführungsform das galvanische Beschichten (oder Elektroplattieren) zu ermöglichen. In verschiedenen Ausführungsformen können die frontseitigen Umverdrahtungsmetallleitungen 150 mehrere Schichten umfassen, zum Beispiel in einer Ausführungsform Cu/Ni, Cu/Ni/Pd/Au, Cu/NiMoP/Pd/Au oder Cu/Sn.
  • Die strukturierte Fotoresistschicht 85 wird abgetrennt, um die leitfähige Keimschicht 80 freizulegen. Die freigelegte, leitfähige Keimschicht 80 und der darunter liegende leitfähige Belag 70 werden weggeätzt (wie durch die Pfeile veranschaulicht wird), zum Beispiel unter Verwendung von Nassätzchemie. Die Struktur auf dieser Stufe wird in 11 veranschaulicht, und sie enthält Kontaktpads 90 und frontseitige Umverdrahtungsmetallleitungen 150.
  • Gemäß 12 wird der rekonstituierte Wafer 5, der das Halbleiter-Modul 100 umfasst, das ausgebildet wird, von der Rückseite her gedünnt, wodurch die mehreren Halbleiter-Chips 20 freigelegt werden. Das Dünnen des rekonstituierten Wafers 5 dünnt in einigen Ausführungsformen möglicherweise auch die mehreren Halbleiter-Chips 20. Das Dünnen wird in verschiedenen Ausführungsformen möglicherweise unter Verwendung eines mechanischen Prozesses, eines chemischen Prozesses, eines chemisch-mechanischen Prozesses durchgeführt.
  • Ein dielektrischer Belag 210 wird über der unteren Oberfläche des rekonstituierten Wafers 5 abgeschieden. Eine rückseitige Isolierschicht 220 kann über dem dielektrischen Belag 210 abgeschieden werden. Eine Abdeckschicht 240 wird über die rückseitige Isolierschicht 220 geschleudert. In einer oder mehreren Ausführungsformen wird möglicherweise eine Hartmaskenschicht 230 auf der rückseitigen Isolierschicht 220 zwischen der rückseitigen Isolierschicht 220 und der Abdeckschicht 240 abgeschieden. Die Hartmaskenschicht 230 kann eine einzelne Schicht sein oder mehrere Schichten umfassen. Die Hartmaskenschicht 230 schützt die mehreren Halbleiter-Chips 20 und die rückseitige Isolierschicht 220 während des Ätzens der Durchsubstratöffnungen. Die Hartmaskenschicht 230 wird möglicherweise auf der Basis der Selektivität gegenüber dem Prozess des Ätzens der Durchsubstratöffnungen ausgewählt. Zum Beispiel wird in einer Ausführungsform ein hochdichtes Plasma (high density plasma) mit einer Fluor-Chemie verwendet, um die Durchsubstratöffnung zu ätzen, und die Hartmaskenschicht 230 umfasst eine SiO2-Hartmaske.
  • Die Abdeckschicht 240 liegt frei und ist strukturiert. Die Hartmaskenschicht 230, die darunter liegende rückseitige Isolierschicht 220 und der dielektrische Belag 210 werden geätzt, um eine untere Oberfläche der mehreren Halbleiter-Chips 20 freizulegen, wobei die strukturierte Abdeckschicht 240 als eine Maske verwendet wird. Die Durchsubstratöffnungen 255 werden innerhalb des Kapselungsmaterials 50 ausgebildet und kontaktieren einen Kontaktpad 90.
  • Wie in 12 veranschaulicht, wird möglicherweise ein Prozess in hochdichtem Plasma (high density plasma) in einer Hochfrequenzplasma-Kammer (RF plasma chamber, radio frequency plasma chamber) verwendet, um Durchsubstratöffnungen 255 im Kapselungsmaterial 50 auszubilden. Ein Schritt des Ätzens wird unter Verwendung eines Fluor basierten Plasmas ausgeführt. Jedoch sind Ätzungen auf Basis von Fluor isotrop und können zu nicht vertikalen Seitenwandungen führen. Daher wird ein Abscheidungsschritt ausgeführt, indem ein gaserzeugendes Polymer in die Plasma-Kammer eingebracht wird. Das gaserzeugende Polymer scheidet eine Polymerschicht auf den freiliegenden Seitenwandungen ab und bildet dadurch eine zeitweilige Blockierschicht für das Ätzen aus. Die Polymerschicht wird nicht auf der freiliegenden unteren Oberfläche des Grabens ausgebildet, was auf die große Energie der auftreffenden Ionen zurückzuführen ist. Jedes Polymer, das auf der unteren Oberfläche des Grabens abgeschieden wird, wird durch die große Energie der auftreffenden Ionen aufgebrochen. Der Durchsubstratöffnungsprozess wird in aufeinanderfolgenden Ätz- und Depositionsschritten ausgeführt. So wird möglicherweise eine vertikale Öffnung produziert. Zum Beispiel umfasst der Fluor-Ätz-Schritt möglicherweise ein SF6-Ätzmittel, wohingegen das gaserzeugende Polymer möglicherweise C4F8 umfasst. Die Ätz- und Depositionsschritte werden möglicherweise viele Male wiederholt, z.B. etwa 100-mal bis zu etwa 500-mal, um die Durchsubstratöffnung 255 auszubilden. In anderen Ausführungsformen werden möglicherweise andere reaktive Ionenätz-Prozesse verwendet. Nach dem Ätz-Schritt umfasst die Durchsubstratöffnung 255 möglicherweise jede geeignete vertikale Form, wie zum Beispiel eine zylindrische, ringförmige, facettierte, grabenförmige usw. Der Endpunkt des Ätzprozesses wird möglicherweise mittels einer Untersuchung (z.B. einer optischen) während des Ätzens bestimmt und kann in einigen Ausführungsformen zeitlich festgelegt sein.
  • Gemäß 13 werden alle verbleibenden Abdeckschichten 240 und Hartmaskenschichten 230 entfernt, wodurch die rückseitige Isolierschicht 220 freigelegt wird. Eine optionale dielektrische Seitenwandschicht wird möglicherweise auf den Seitenwandungen der Durchsubstratöffnung 255 abgeschieden. Ein Sperrbelag 235 wird abgeschieden, bevor die Durchsubstratöffnung 255 mit einem leitfähigen Füllmaterial gefüllt wird. Der Sperrbelag 235 ist konform und umfasst möglicherweise eine einzelne Schicht aus zum Beispiel Ta, TaN, W, WN, WCN, WSi, Ti, TiN und/oder Ru. Der Sperrbelag 235 wird möglicherweise als Sperrschicht verwendet, um Metall daran zu hindern, in die darunter liegenden mehreren Halbleiter-Chips 20 und/oder in das Kapselungsmaterial 50 zu diffundieren. Der Sperrbelag 235 wird zum Beispiel möglicherweise unter Verwendung des Hochfrequenz-Magnetronsputterns (RF magnetron sputtering) abgeschieden. Eine rückseitige Keimschicht 245 kann optional über dem Sperrbelag 235 abgeschieden werden. Diese rückseitige Keimschicht 245 wird möglicherweise konform abgeschieden, zum Beispiel unter Verwendung von PVD-Sputtern (physical vapor deposition, physikalische Gasphasenabscheidung) oder eines metall-organischen CVD-Prozesses (MOCVD, metal-organic chemical vapour deposition, metall-organische Gasphasenabscheidung).
  • Ein Fotoresistbelag 265 wird auf der rückseitigen Oberfläche des rekonstituierten Wafers 5 abgeschieden. In verschiedenen Ausführungsformen ist die Fotoresistschicht 265 eine dicke Schicht von Fotoresist, die eine Dicke von einigen Mikrometern umfasst. Die Fotoresistschicht 265 wird unter Verwendung eines fotolithografischen Schrittes strukturiert. Der fotolithografische Schritt wird durch eine Maske mit Strukturen für die rückseitigen Umverdrahtungsleitungen und Durchsubstratöffnungen 255 durchgeführt. Der fotolithografische Schritt legt den Sperrbelag 235 und die optionale, rückseitige Keimschicht 245 frei.
  • Wie in 13 veranschaulicht, wird eine rückseitige Umverdrahtungsschicht durch Abscheiden eines rückseitigen, leitfähigen Füllmaterials 250 auf der rückseitigen Keimschicht 245 ausgebildet, zum Beispiel unter Verwendung eines galvanischen Beschichtungsprozesses. Das rückseitige, leitfähige Füllmaterial 250 wird somit zwischen der strukturierten Fotoresistschicht 265 abgeschieden. Das rückseitige, leitfähige Füllmaterial 250 wird somit sowohl innerhalb der Durchsubstratöffnung 255 und auf Strukturen für rückseitige Umverdrahtungsleitungen abgeschieden. In einigen Ausführungsformen füllt das rückseitige, leitfähige Füllmaterial 250 möglicherweise die Durchsubstratöffnung 255 zum Teil.
  • In einer Ausführungsform umfasst das rückseitige, leitfähige Füllmaterial 250 Kupfer. In einer oder mehreren Ausführungsformen umfasst das rückseitige, leitfähige Füllmaterial 250 Kupfer, Silber, Gold, Nickel, Zink und/oder Platin. In einer anderen Ausführungsform umfasst das rückseitige, leitfähige Füllmaterial 250 Wolfram. Falls das rückseitige, leitfähige Füllmaterial 250 Wolfram umfasst, wird vorzugsweise eine doppelschichtige Keimschicht, die CVD-Titannitrid und Silizium dotiertes Wolfram umfasst, verwendet. Ähnlich wird in einigen Ausführungsformen möglicherweise dotiertes Poly-Silizium, Silber, Gold und/oder Aluminium im Innern der DurchsubstratÖffnung 255 abgeschieden, um die vertikalen Substrat-Durchkontaktierungen 260 auszubilden. Die verbleibende Fotoresistschicht 265 wird abgetrennt, um die rückseitige Keimschicht 245 freizulegen. Die rückseitige Keimschicht 245 und der Sperrbelag 235 werden mit Nass- oder Trockenätzen entfernt, um die darunter liegende, rückseitige Isolierschicht 220 freizulegen.
  • In einer alternativen Ausführungsform wird das rückseitige, leitfähige Füllmaterial 250 möglicherweise unter Verwendung eines subtraktiven Ätzprozesses abgeschieden und strukturiert. In einer weiteren Ausführungsform wird die rückseitige Umverdrahtungsschicht möglicherweise direkt gedruckt, zum Beispiel unter Verwendung von Schablonendruck oder Siebdruck.
  • Der rekonstituierte Wafer 5 wird vereinzelt, wodurch das einzelne Halbleiter-Modul 100 ausgebildet wird. Das Halbleiter-Modul 100 umfasst mehrere Kontaktpads 90 zum Ausbilden externer Kontakte.
  • Das so ausgebildete Halbleiter-Modul 100 wird möglicherweise vor dem anschließenden Packaging getestet. Zum Beispiel wird möglicherweise eine Testsonde über den Kontaktpads 90 angebracht, um defekte Einheiten zu ermitteln.
  • Das so ausgebildete Halbleiter-Modul 100 wird möglicherweise direkt verwendet und in einigen Ausführungsformen auf einer Platine (engl. circuit board) montiert. In anderen Ausführungsformen wird das Halbleiter-Modul 100 möglicherweise über einem Leadframe, Cliprahmen und anderen geeigneten Substraten gehäust, um ein Halbleiter-Package auszubilden. Ausführungsformen der Erfindung enthalten das Ausbilden aller geeigneten Package-Typen, zum Beispiel solche, die kompatibel zu JEDEC-Standards sind. Beispiele sind u.a. Transistor Outline Packages, Small Outline Packages, Thin Small Outline Packages, Thin Shrink Small Outline Packages, Single In-line Packages und andere.
  • Gemäß 14 wird ein Halbleiter-Modul 100, das zum Beispiel wie in 13 ausgebildet ist, über einem Leadframe 300 platziert. Das Halbleiter-Modul 100 wird möglicherweise am Leadframe 300 unter Verwendung einer Die-Attach-Schicht 280 angebracht, die in einer Ausführungsform isolierend sein kann. In einigen Ausführungsformen ist die Die-Attach-Schicht 280 möglicherweise leitfähig, zum Beispiel kann sie eine nanoleitfähige Paste umfassen. In alternativen Ausführungsformen wird das rückseitige, leitfähige Füllmaterial 250 möglicherweise an den Leadframe 300 gelötet, so dass die Die-Attach-Schicht 280 ein lötfähiges Material ist.
  • In einer Ausführungsform umfasst die Die-Attach-Schicht 280 ein Polymer, wie zum Beispiel ein Cyanid-Ester- oder Epoxidharz-Material, und sie umfasst möglicherweise Silberpartikel. In einer Ausführungsform wird die Die-Attach-Schicht 280 möglicherweise als leitfähige Teilchen in einer Polymer-Matrix aufgebracht, um so nach dem Aushärten ein Verbundmaterial auszubilden. In einer alternativen Ausführungsform wird möglicherweise eine leitfähige Nano-Paste wie eine Silber-Nano-Paste aufgebracht. Alternativ umfasst in einer anderen Ausführungsform die Die-Attach-Schicht 280 ein Lot, wie zum Beispiel ein Blei-Zinn-Material. In verschiedenen Ausführungsformen kann jedes geeignete, leitfähige, klebende Material, das Metalle oder Metalllegierungen enthält, wie zum Beispiel Aluminium, Titan, Gold, Silber, Kupfer, Palladium, Platin, Nickel, Chrom oder Nickel-Vanadium, zum Ausbilden der Die-Attach-Schicht 280 verwendet werden.
  • Die Die-Attach-Schicht 280 wird möglicherweise in gesteuerten Mengen unter dem Halbleiter-Modul 100 aufdosiert. Eine Die-Attach-Schicht 280, die ein Polymer aufweist, härtet möglicherweise bei etwa 125 °C bis etwa 200 °C aus, wohingegen eine Die-Attach-Schicht 280 auf Lotbasis möglicherweise bei 250 °C bis etwa 350 °C aushärtet. Unter Verwendung der Die-Attach-Schicht 280 wird das Halbleiter-Modul 100 am Die-Paddle 310 des Leadframe 300 angebracht.
  • In einer oder mehreren Ausführungsformen werden die Kontaktpads 90 auf dem Halbleiter-Modul 100 mit dem Leadframe 300 unter Verwendung von Drahtbonds 330 und einem Drahtbond-Prozess verbunden. Die Drahtbonds 330 werden möglicherweise an die Leads 320 des Leadframe 300 und die Kontaktpads 90 unter Verwendung von Lotkugeln 340 angelötet.
  • In einer oder mehreren Ausführungsformen umfassen die Drahtbonds 330 möglicherweise Aluminium oder Kupfer. Die Dicke solcher Aluminiumdrähte kann etwa 10 µm (Mikrometer) bis etwa 1000 µm (Mikrometer) in einer oder mehreren Ausführungsformen betragen. In einer anderen Ausführungsform umfassen die Drahtbonds 330 möglicherweise Gold. Die Dicke solcher Golddrähte kann etwa 10 µm (Mikrometer) bis etwa 100 µm (Mikrometer) betragen.
  • In einer oder mehreren Ausführungsformen werden möglicherweise High-Speed Drahtbond-Vorrichtungen eingesetzt, um die Zeit für das Ausbilden der Drahtbonds 330 zu minimieren. Möglicherweise werden Bilderkennungssysteme verwendet, um das Halbleiter-Modul 100 während des Draht-Bond-Prozesses in einigen Ausführungsformen auszurichten.
  • In verschiedenen Ausführungsformen wird möglicherweise Ball-Bonden oder Wedge-Bonden verwendet, um die Drahtbonds 330 anzubringen. In verschiedenen Ausführungsformen werden die Drahtbonds 330 möglicherweise unter Verwendung des Thermosonic-Bondens, Ultraschall-Bondens oder Thermokompressions-Bondens ausgebildet. Thermosonic-Bonden nutzt Temperatur, Ultraschall und geringen Druck sowie Ball- bzw. Wedge-Verfahren. Ultraschall-Bonden nutzt Ultraschall und geringen Druck sowie nur das Wedge-Verfahren. Thermo-Kompressions-Bonden nutzt Temperatur und hohen Druck sowie nur das Wedge-Verfahren.
  • Zum Beispiel kann in einem Fall das Thermosonic-Bonden mit Gold- oder Kupferdrähten verwendet werden. Zwei Drahtbonds werden für jede Verbindung ausgebildet, eine an den Kontaktpads 90 des Halbleiter-Moduls 100 und eine andere an einem Lead der mehreren Leads 320 des Leadframe 300. Die Temperatur des Bondens, Ultraschallenergie sowie Bondkraft und -zeit müssen möglicherweise genau gesteuert werden, um eine zuverlässige Verbindung vom Halbleiter-Modul 100 zum Leadframe 300 auszubilden.
  • In einer oder mehreren Ausführungsformen werden für den Drahtbond-Prozess möglicherweise ein Lötflussmittel und ein Lötmaterial abgeschieden. Das Lötmaterial wird möglicherweise galvanisch abgeschieden, obwohl in anderen Ausführungsformen möglicherweise auch andere Prozesse, wie zum Beispiel stromlose Beschichtungs- oder Depositionsprozesse, zum Beispiel Gasphasenabscheidung, verwendet werden. Das Lötmaterial kann eine einzelne Schicht sein oder mehrere Schichten mit unterschiedlichen Zusammensetzungen umfassen. Zum Beispiel umfasst in einer Ausführungsform das Lötmaterial möglicherweise ein Bleischicht (Pb), gefolgt von einer Zinnschicht (Sn) . In einer anderen Ausführungsform wird möglicherweise ein SnAg als Lötmaterial abgeschieden. Andere Beispiele sind u.a. SnPbAg, SnPb, PbAg, PbIn und bleifreie Materialien, wie zum Beispiel SnBi, SnAgCu, SnTn oder SiZn. In verschiedenen Ausführungsformen werden möglicherweise andere geeignete Materialien abgeschieden.
  • Um die in 14 veranschaulichten Lotkugeln 340 auszubilden, wird möglicherweise eine Wärmebehandlung durchgeführt. Die Wärmebehandlung schmilzt das Lotmaterial auf, und die Wärme formt die Lotkugeln 340. Zum Beispiel werden in einer Ausführungsform, wenn nach dem Aufschmelzen die Pb/Sb-Schicht abgeschieden wird, stark bleihaltige Legierungen ausgebildet, darunter 95 Pb/5 Sn (95/5) oder 90 Pb/10 Sn (95/10), mit Schmelztemperaturen von mehr als 300°C. In einer anderen Ausführungsform wird eutektisches 63 Pb/37 Sn (63/37) mit einer Schmelztemperatur von 183 °C ausgebildet. Ähnlich werden möglicherweise bleifreie Lotkugeln 340 mit einer Zusammensetzung von 97,5 Sn/2,6 Ag (97,5/2,5) ausgebildet. Die Lotkugeln 340 umfassen ein homogenes Material und weisen eine genau definierte Schmelztemperatur auf. Zum Beispiel sind die hochschmelzenden Pb/Sn-Legierungen zuverlässige Metallmaterialien, die widerstandsfähig gegenüber Materialermüdung sind. Auch diffundiert das Metall der Kontaktpads 90 und vermischt sich während der Wärmebehandlung möglicherweise in einigen Ausführungsformen.
  • Gemäß 15 wird ein äußeres Kapselungsmaterial 350 über dem Halbleiter-Modul 100 und dem Leadframe 300 aufgebracht. In einer oder mehreren Ausführungsformen wird das äußere Kapselungsmaterial 350 möglicherweise unter Verwendung eines Formpress-Prozesses aufgebracht. Beim Formpressen (engl. compression molding) wird das äußere Kapselungsmaterial 350 möglicherweise in einem Vergusshohlraum (engl. molding cavity) platziert, anschließend wird der Vergusshohlraum verschlossen, um das äußere Kapselungsmaterial 350 zu verdichten. Formpressen wird möglicherweise verwendet, wenn eine einzelne Struktur ausgebildet wird. In einer alternativen Ausführungsform wird das äußere Kapselungsmaterial 350 möglicherweise unter Verwendung eines Transferpress-Prozesses (engl. transfer molding) aufgebracht. In anderen Ausführungsformen wird das äußere Kapselungsmaterial 350 möglicherweise unter Verwendung von Spritzguss, Granulatspritzguss, Pulverschmelzverfahren oder Gießen aufgebracht. Alternativ wird das äußere Kapselungsmaterial 350 möglicherweise unter Verwendung eines Druck-Prozesses, wie zum Beispiel des Schablonen- oder Siebdrucks, aufgebracht. Ein Härtungsprozess wird möglicherweise ausgeführt, um ein Leadframe-Package auszubilden.
  • Die 16 - 17 veranschaulichen alternative Ausführungsformen zum Ausbilden des Halbleiter-Packages.
  • Anders als in der in den 14 - 15 veranschaulichten Ausführungsform umfassen in dieser Ausführungsform die Verbindungen zwischen dem Halbleiter-Modul 100 und dem Leadframe 300 Clips 370. Die Clips 370 werden möglicherweise an den Leads 320 des Leadframe 300 unter Verwendung einer Clip-Klebeschicht 360 angebracht, z.B. eines Lötmaterials oder einer leitfähigen Paste. Wie oben beschrieben wird ein äußeres Kapselungsmaterial 350 über dem Leadframe 300 und dem Halbleiter-Modul 100 ausgebildet, nachdem die Clips 370 angebracht worden sind.
  • In weiteren alternativen Ausführungsformen können die Verbindungen zwischen dem Halbleiter-Modul 100 und dem Leadframe 300 unter Verwendung eines galvanischen Prozesses ausgebildet werden (elektro-chemisches Abscheiden).
  • Ausführungsformen der Erfindung enthalten auch das Ausbilden eines ersten fertigen Produkts, wie zum Beispiel des in verschiedenen Ausführungsformen beschriebenen Halbleiter-Moduls 100. Das erste fertige Produkt ist möglicherweise ein Package, welches zu standardisierten Packaging-Modulen nicht konform ist, zum Beispiel nicht gemäß den JEDEC-Standards. Obwohl das erste fertige Produkt möglicherweise an manche Kunden direkt verkauft wird, wird es möglicherweise weiter innerhalb eines Leadframe gehäust, um ein zweites fertiges Package auszubilden, wie zum Beispiel das oben in verschiedenen Ausführungsformen beschriebene Leadframe-Package. Das zweite fertige Package ist möglicherweise konform zu standardisiertem Packaging, wie zum Beispiel gemäß den JEDEC-Standards. Jedoch weisen sowohl das erste wie das zweite fertige Package ähnliche Funktion und Wirkungsweise auf. Zum Beispiel weist das Leadframe-Package möglicherweise keine zusätzlichen Halbleiter-Bauelemente neben denen im Halbleiter-Modul 100 auf.
  • 18 veranschaulicht ein nicht erfindungsgemäßes Beispiel des Halbleiter-Packages, indem sie ein gestapeltes Halbleiter-Package-in-Package veranschaulicht.
  • In diesem Beispiel enthält das Halbleiter-Modul 100 möglicherweise eine Stapelung mehrerer Halbleiter-Chips 20, die möglicherweise durch vertikale Durchkontaktierungen verbunden sind. Das Halbleiter-Modul 100 wird über dem Leadframe 300 angeordnet und zum Ausbilden eines standardisierten Leadframe-Packages gehäust.
  • Verschiedene Modifikationen und Kombinationen der veranschaulichenden Ausführungsformen wie auch anderer Ausführungsformen der Erfindung werden sich für Fachleute unter Bezugnahme auf die Beschreibung ergeben. Zur Veranschaulichung: Die in den 1 - 17 beschriebenen Ausführungsformen können miteinander kombiniert werden.

Claims (15)

  1. Halbleitervorrichtung, umfassend: einen Leadframe (300), welcher mehrere Leads (320) und ein Die-Paddle (310) umfasst; ein Halbleiter-Modul (100), welches an einer Oberfläche des Die-Paddle (310) des Leadframe (300) angebracht ist, wobei das Halbleiter-Modul (100) einen ersten Halbleiter-Chip (20, 21, 25) und einen zweiten Halbleiter-Chip (20, 21,25) umfasst, welche in ein erstes Kapselungsmaterial (50) eingebettet sind, wobei die Halbleiter-Chips (20,21,25) derart lateral nebeneinander angeordnet sind, dass laterale Oberflächen der Halbleiter-Chips (20,21,25) welche senkrecht zur Oberfläche des Die-Paddle (310) angeordnet sind, einander gegenüberliegen, wobei das Halbleiter-Modul (100) mehrere mit dem ersten Halbleiter-Chip (20,21,25) gekoppelte Kontaktpads (90) umfasst; mehrere Verbindungen (330), welche die mehreren Kontaktpads (90) mit den mehreren Leads (320) koppeln; und ein zweites Kapselungsmaterial (350), welches auf dem Halbleiter-Modul (100) und dem Leadframe (300) angeordnet ist, wobei der erste Halbleiter-Chip (20,21,25) und der zweite Halbleiter-Chip (20,21,25) durch eine an ihren Vorderseiten, in der Nähe einer ersten Seite des Halbleiter-Moduls (100) angeordnete Umverdrahtungsschicht gekoppelt sind, wobei die Vorderseiten von dem Die-Paddle (310) wegweisen, wobei die Umverdrahtungsschicht eine gemeinsame Passivierungsschicht (60) und gemeinsame Umverdrahtungsleitungen (150) der Halbleiter-Chips (20,21,25) aufweist, und wobei die Umverdrahtungsleitungen (150) von dem zweiten Kapselungsmaterial (350) bedeckt sind.
  2. Halbleitervorrichtung nach Anspruch 1, wobei der erste Halbleiter-Chip (20,21,25) ferner mit dem zweiten Halbleiter-Chip (20,21,25) durch rückseitige, in der Nähe einer zweiten Seite des Halbleiter-Moduls (100) angeordnete Umverdrahtungsleitungen gekoppelt ist.
  3. Halbleitervorrichtung nach einem der vorhergehenden Ansprüche, wobei die Gesamtanzahl der mehreren Leads (320) sich von der Gesamtanzahl der mehreren Kontaktpads (90) des Halbleiter-Moduls (100) unterscheidet.
  4. Halbleitervorrichtung nach einem der vorhergehenden Ansprüche, wobei die mehreren Leads (320) mit den mehreren Kontaktpads (90) unter Verwendung von Draht-Bonden oder von Lead-Bonden gekoppelt sind.
  5. Halbleitervorrichtung nach einem der Ansprüche 1 bis 3, wobei die mehreren Leads (320) mit den mehreren Kontaktpads (90) unter Verwendung von Clip-Bonden gekoppelt sind.
  6. Halbleitervorrichtung, umfassend: einen Leadframe (300), welcher mehrere Leads (320) und ein Die-Paddle (310) umfasst; ein Halbleiter-Modul (100), welches an einer Oberfläche des Die-Paddle (310) des Leadframe (300) angeordnet ist, wobei das Halbleiter-Modul (100) einen ersten Halbleiter-Chip (20,21,25) und einen zweiten Halbleiter-Chip (20,21,25) umfasst, wobei die Halbleiter-Chips (20) derart lateral nebeneinander angeordnet sind, dass laterale Oberflächen der Halbleiter-Chips (20,21,25) welche senkrecht zur Oberfläche des Die-Paddle (310) angeordnet sind, einander gegenüberliegen, wobei das Halbleiter-Modul (100) mehrere mit dem ersten Halbleiter-Chip (20,21,25) gekoppelte Kontaktpads (90) umfasst, wobei das Halbleiter-Modul (100) ein Embedded Wafer Level Package ist; und ein auf dem Halbleiter-Modul (100) und dem Leadframe (300) angeordnetes Kapselungsmaterial (350), wobei der erste Halbleiter-Chip (20) und der zweite Halbleiter-Chip (20) durch eine an ihren Vorderseiten, in der Nähe einer ersten Seite des Halbleiter-Moduls (100) angeordnete Umverdrahtungsschicht gekoppelt sind, wobei die Vorderseiten von dem Die-Paddle (310) wegweisen, wobei die Umverdrahtungsschicht eine gemeinsame Passivierungsschicht (60) und gemeinsame Umverdrahtungsleitungen (150) der Halbleiter-Chips (20,21,25) aufweist, und wobei die Umverdrahtungsleitungen (150) von dem Kapselungsmaterial (350) bedeckt sind.
  7. Halbleitervorrichtung nach Anspruch 6, wobei der erste Halbleiter-Chip (20) ferner mit dem zweiten Halbleiter-Chip (20,21,25) durch rückseitige, in der Nähe einer zweiten Seite des Halbleiter-Moduls (100) angeordnete Umverdrahtungsleitungen gekoppelt ist.
  8. Halbleitervorrichtung nach einem der Ansprüche 6 oder 7, wobei der erste Halbleiter-Chip (20,21,25) ein diskreter Leistungstransistor ist.
  9. Halbleitervorrichtung nach einem der Ansprüche 6 bis 8, wobei die mehreren Kontaktpads (90) ein Source-Kontaktpad, ein Drain-Kontaktpad und ein Steuer-Kontaktpad umfassen.
  10. Halbleitervorrichtung nach Anspruch 9, wobei das Source-Kontaktpad mit einer ersten Seite des ersten Halbleiter-Chips (20,21,25) gekoppelt ist, und wobei das Drain-Kontaktpad mit einer gegenüberliegenden, zweiten Seite des ersten Halbleiter-Chips (20,21,25) gekoppelt ist.
  11. Halbleitervorrichtung nach einem der Ansprüche 6 bis 10, wobei die Anordnung der mehreren Leads (320) unabhängig von der Anordnung der mehreren Kontaktpads (90) auf dem ersten Halbleiter-Chip (20,21,25) ist.
  12. Halbleitervorrichtung nach einem der Ansprüche 6 bis 11, wobei die Gesamtanzahl der mehreren Leads (320) sich von der Gesamtanzahl der mehreren Kontaktpads (90) des Halbleiter-Moduls (100) unterscheidet.
  13. Verfahren zum Ausbilden einer Halbleitervorrichtung, wobei das Verfahren umfasst: Bereitstellen eines Leadframe (300), welcher mehrere Leads (320) und ein Die-Paddle (310) umfasst; Bereitstellen eines Halbleiter-Moduls (100), welches einen ersten Halbleiter-Chip (20,21,25) und einen zweiten Halbleiter-Chip (20,21,25) umfasst, welche in ein erstes Kapselungsmaterial (50) eingebettet sind, wobei das Halbleiter-Modul (100) mehrere mit dem ersten Halbleiter-Chip (20) gekoppelte Kontaktpads (90) umfasst; Anbringen des Halbleiter-Moduls (100) an dem Die-Paddle (310) des Leadframe (300); elektrisches Koppeln der mehreren Kontaktpads (90) mit den mehreren Leads (320); und Kapseln des Halbleiter-Moduls (100) und des Leadframe (300) mit einem zweiten Kapselungsmaterial (350), wobei das Halbleiter-Modul (100) ferner eine vorderseitige Umverdrahtungsschicht umfasst, welche den ersten Halbleiter-Chip (20,21,25) mit dem zweiten Halbleiter-Chip (20,21,25) koppelt, wobei die Umverdrahtungsschicht eine gemeinsame Passivierungsschicht (60) und gemeinsame Umverdrahtungsleitungen (150) der Halbleiter-Chips (20,21,25) aufweist, und wobei das zweite Kapselungsmaterial (350) die Umverdrahtungsleitungen bedeckt.
  14. Verfahren nach Anspruch 13, wobei das elektrische Koppeln einen galvanischen Prozess verwendet.
  15. Verfahren nach einem der Ansprüche 13 oder 14, wobei das Halbleiter-Modul (100) ferner rückseitige Umverdrahtungsleitungen umfasst, welche den ersten Halbleiter-Chip (20,21,25) mit dem zweiten Halbleiter-Chip (20,21,25) koppeln, und wobei die rückseitigen Umverdrahtungsleitungen auf einer den vorderseitigen Umverdrahtungsleitungen (150) gegenüberliegenden Seite des Halbleiter-Moduls (100) angeordnet sind.
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