DE102011122918B3 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung Download PDF

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Publication number
DE102011122918B3
DE102011122918B3 DE102011122918.7A DE102011122918A DE102011122918B3 DE 102011122918 B3 DE102011122918 B3 DE 102011122918B3 DE 102011122918 A DE102011122918 A DE 102011122918A DE 102011122918 B3 DE102011122918 B3 DE 102011122918B3
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DE
Germany
Prior art keywords
wafer
main surface
region
circuit pattern
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102011122918.7A
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German (de)
English (en)
Inventor
Yoshihiro Tsukahara
Shinsuke Watanabe
Ko Kanaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of DE102011122918B3 publication Critical patent/DE102011122918B3/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554External layer
    • H01L2224/0556Disposition
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    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01Chemical elements
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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    • H01L2924/351Thermal stress

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE102011122918.7A 2010-07-29 2011-07-13 Halbleitervorrichtung Expired - Fee Related DE102011122918B3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-170570 2010-07-29
JP2010170570A JP5521862B2 (ja) 2010-07-29 2010-07-29 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE102011122918B3 true DE102011122918B3 (de) 2016-05-19

Family

ID=45525895

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102011122918.7A Expired - Fee Related DE102011122918B3 (de) 2010-07-29 2011-07-13 Halbleitervorrichtung
DE102011079105A Withdrawn DE102011079105A1 (de) 2010-07-29 2011-07-13 Halbleitervorrichtung und Verfahren zum Herstellen derselben

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE102011079105A Withdrawn DE102011079105A1 (de) 2010-07-29 2011-07-13 Halbleitervorrichtung und Verfahren zum Herstellen derselben

Country Status (5)

Country Link
US (1) US8728866B2 (enrdf_load_stackoverflow)
JP (1) JP5521862B2 (enrdf_load_stackoverflow)
CN (1) CN102347243B (enrdf_load_stackoverflow)
DE (2) DE102011122918B3 (enrdf_load_stackoverflow)
TW (1) TWI446429B (enrdf_load_stackoverflow)

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CN103227116B (zh) * 2013-03-29 2016-01-20 日月光半导体制造股份有限公司 透光壳体及其制造方法与应用其的光学组件
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
JP6221736B2 (ja) * 2013-12-25 2017-11-01 三菱電機株式会社 半導体装置
JP6215755B2 (ja) 2014-04-14 2017-10-18 ルネサスエレクトロニクス株式会社 半導体装置
TWI566288B (zh) * 2014-07-14 2017-01-11 矽品精密工業股份有限公司 切割用載具及切割方法
JP6314731B2 (ja) * 2014-08-01 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
CN107851962B (zh) * 2015-07-28 2020-05-01 日本电信电话株式会社 光模块
JP6350759B2 (ja) * 2015-08-18 2018-07-04 三菱電機株式会社 半導体装置
US10393532B2 (en) * 2015-10-20 2019-08-27 International Business Machines Corporation Emergency responsive navigation
US10825694B2 (en) * 2017-02-02 2020-11-03 Hitachi Chemical Company, Ltd. Method for manufacturing electronic component, resin composition for temporary protection, and resin film for temporary protection
JP2019192729A (ja) * 2018-04-23 2019-10-31 株式会社村田製作所 半導体装置
DE112018007677B4 (de) * 2018-05-28 2023-10-12 Mitsubishi Electric Corporation Verfahren zur Herstellung eines Halbleitergerätes
JP7034105B2 (ja) 2019-01-18 2022-03-11 三菱電機株式会社 電力用半導体装置の製造方法、電力用半導体装置および電力変換装置
KR102785840B1 (ko) 2019-12-13 2025-03-26 삼성전자주식회사 반도체 패키지
US11948893B2 (en) * 2021-12-21 2024-04-02 Qorvo Us, Inc. Electronic component with lid to manage radiation feedback

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JP2501279B2 (ja) 1991-11-29 1996-05-29 株式会社東芝 半導体パッケ―ジ
JP2001024079A (ja) 1999-07-05 2001-01-26 Seiko Epson Corp 電子部品の封止構造
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US20080081398A1 (en) * 2006-10-02 2008-04-03 Fionix Inc. Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same

Also Published As

Publication number Publication date
CN102347243B (zh) 2014-08-20
CN102347243A (zh) 2012-02-08
US8728866B2 (en) 2014-05-20
TWI446429B (zh) 2014-07-21
TW201205656A (en) 2012-02-01
DE102011079105A1 (de) 2012-04-12
JP2012033615A (ja) 2012-02-16
US20120025366A1 (en) 2012-02-02
JP5521862B2 (ja) 2014-06-18

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