DE10084545T1 - Spannungsversorgungsschaltung mit niedrigem Leckstrom für eine integrierte Schaltung zur Verwendung bei einem Fortgeschrittenen CMOS-Prozess - Google Patents

Spannungsversorgungsschaltung mit niedrigem Leckstrom für eine integrierte Schaltung zur Verwendung bei einem Fortgeschrittenen CMOS-Prozess

Info

Publication number
DE10084545T1
DE10084545T1 DE10084545T DE10084545T DE10084545T1 DE 10084545 T1 DE10084545 T1 DE 10084545T1 DE 10084545 T DE10084545 T DE 10084545T DE 10084545 T DE10084545 T DE 10084545T DE 10084545 T1 DE10084545 T1 DE 10084545T1
Authority
DE
Germany
Prior art keywords
leakage current
current supply
cmos process
low leakage
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10084545T
Other languages
English (en)
Other versions
DE10084545B4 (de
Inventor
Bart R Mcdaniel
Lawrence T Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp of America
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10084545T1 publication Critical patent/DE10084545T1/de
Application granted granted Critical
Publication of DE10084545B4 publication Critical patent/DE10084545B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
DE10084545T 1999-04-30 2000-04-20 Spannungsversorgungsschaltung mit niedrigem Leckstrom für eine integrierte Schaltung zur Verwendung bei einem Fortgeschrittenen CMOS-Prozess Expired - Lifetime DE10084545B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/302,729 1999-04-30
US09/302,729 US6166985A (en) 1999-04-30 1999-04-30 Integrated circuit low leakage power circuitry for use with an advanced CMOS process
PCT/US2000/010820 WO2000067380A1 (en) 1999-04-30 2000-04-20 Integrated circuit low leakage power circuitry for use with an advanced cmos process

Publications (2)

Publication Number Publication Date
DE10084545T1 true DE10084545T1 (de) 2002-04-11
DE10084545B4 DE10084545B4 (de) 2009-07-02

Family

ID=23168972

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10084545T Expired - Lifetime DE10084545B4 (de) 1999-04-30 2000-04-20 Spannungsversorgungsschaltung mit niedrigem Leckstrom für eine integrierte Schaltung zur Verwendung bei einem Fortgeschrittenen CMOS-Prozess

Country Status (8)

Country Link
US (1) US6166985A (de)
JP (1) JP4643025B2 (de)
KR (1) KR100479150B1 (de)
CN (1) CN100375388C (de)
AU (1) AU4481000A (de)
DE (1) DE10084545B4 (de)
GB (1) GB2363685B (de)
WO (1) WO2000067380A1 (de)

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JP5240792B2 (ja) * 2001-06-05 2013-07-17 ルネサスエレクトロニクス株式会社 半導体装置
US7102254B2 (en) * 2002-01-23 2006-09-05 Koninklijke Philips Electronics N.V. Integrated circuit and battery powered electronic device
JP4388274B2 (ja) * 2002-12-24 2009-12-24 株式会社ルネサステクノロジ 半導体記憶装置
US20040128574A1 (en) * 2002-12-31 2004-07-01 Franco Ricci Reducing integrated circuit power consumption
US7027346B2 (en) * 2003-01-06 2006-04-11 Texas Instruments Incorporated Bit line control for low power in standby
US7055007B2 (en) * 2003-04-10 2006-05-30 Arm Limited Data processor memory circuit
KR100992177B1 (ko) 2003-05-07 2010-11-04 모사이드 테크놀로지스 코포레이션 파워 아일랜드를 사용한 집적 회로의 파워 관리
US7227404B2 (en) * 2003-09-15 2007-06-05 Texas Instruments Incorporated Method for preventing regulated supply undershoot in state retained latches of a leakage controlled system using a low drop out regulator
US7212462B1 (en) * 2003-11-04 2007-05-01 Xilinx, Inc. Structure and method for suppressing sub-threshold leakage in integrated circuits
JP2005157620A (ja) * 2003-11-25 2005-06-16 Matsushita Electric Ind Co Ltd 半導体集積回路
US7126861B2 (en) * 2003-12-30 2006-10-24 Intel Corporation Programmable control of leakage current
US7177176B2 (en) * 2004-06-30 2007-02-13 Intel Corporation Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength
KR100604876B1 (ko) * 2004-07-02 2006-07-31 삼성전자주식회사 다양한 ｐｖｔ 변화에 대해서도 안정적인 버츄얼 레일스킴을 적용한 ｓｒａｍ 장치
US7164616B2 (en) * 2004-12-20 2007-01-16 Intel Corporation Memory array leakage reduction circuit and method
JP4660280B2 (ja) * 2005-05-25 2011-03-30 株式会社東芝 半導体記憶装置
TW200707177A (en) * 2005-08-08 2007-02-16 Ind Tech Res Inst Leakage current control circuit with a single low voltage power supply and method thereof
US7852113B2 (en) * 2005-08-16 2010-12-14 Novelics, Llc. Leakage control
US7271615B2 (en) * 2005-08-16 2007-09-18 Novelics, Llc Integrated circuits with reduced leakage current
US7728621B2 (en) 2005-08-16 2010-06-01 Novelics, Llc Block-by-block leakage control and interface
JP4865503B2 (ja) * 2006-07-14 2012-02-01 日本電信電話株式会社 リーク電流低減回路
US7447101B2 (en) * 2006-12-22 2008-11-04 Fujitsu Limited PG-gated data retention technique for reducing leakage in memory cells
US7414878B1 (en) * 2007-05-04 2008-08-19 International Business Machines Corporation Method for implementing domino SRAM leakage current reduction
KR101799482B1 (ko) * 2010-12-29 2017-11-20 삼성전자주식회사 기입 어시스트 회로를 포함하는 정적 메모리 장치
US20130107651A1 (en) 2011-10-27 2013-05-02 Cold Brick Semiconductor, Inc. Semiconductor device with reduced leakage current and method for manufacture the same
US9939883B2 (en) * 2012-12-27 2018-04-10 Nvidia Corporation Supply-voltage control for device power management
US8975934B2 (en) 2013-03-06 2015-03-10 Qualcomm Incorporated Low leakage retention register tray
US9390787B2 (en) * 2013-03-15 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Biasing bulk of a transistor
WO2014158200A1 (en) * 2013-03-25 2014-10-02 Cold Brick Semiconductor, Inc. Semiconductor device with reduced leakage current and method for manufacture the same
US10431269B2 (en) 2015-02-04 2019-10-01 Altera Corporation Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration
IT201600121631A1 (it) * 2016-11-30 2018-05-30 St Microelectronics Srl Dispositivo di memoria a cambiamento di fase con un circuito di pilotaggio di linea di parola a elevata velocita'
US10879898B2 (en) 2018-01-23 2020-12-29 Samsung Electronics Co., Ltd. Power gating circuit for holding data in logic block
CN109741778A (zh) * 2018-12-29 2019-05-10 西安紫光国芯半导体有限公司 一种dram输出驱动电路及其减小漏电的方法

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KR100253647B1 (ko) * 1997-02-22 2000-04-15 윤종용 전력감소회로
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Also Published As

Publication number Publication date
GB0125644D0 (en) 2001-12-19
KR20020042759A (ko) 2002-06-07
DE10084545B4 (de) 2009-07-02
JP2002543731A (ja) 2002-12-17
US6166985A (en) 2000-12-26
AU4481000A (en) 2000-11-17
KR100479150B1 (ko) 2005-03-25
GB2363685B (en) 2004-06-02
JP4643025B2 (ja) 2011-03-02
GB2363685A (en) 2002-01-02
CN100375388C (zh) 2008-03-12
CN1354908A (zh) 2002-06-19
WO2000067380A1 (en) 2000-11-09

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R082 Change of representative
R081 Change of applicant/patentee

Owner name: SONY CORPORATION OF AMERICA, NEW YORK, US

Free format text: FORMER OWNER: INTEL CORPORATION, SANTA CLARA, CALIF., US

Effective date: 20150212

R071 Expiry of right