CN2775840Y - 一种无侧引脚的芯片封装结构 - Google Patents

一种无侧引脚的芯片封装结构 Download PDF

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CN2775840Y
CN2775840Y CN 200420107585 CN200420107585U CN2775840Y CN 2775840 Y CN2775840 Y CN 2775840Y CN 200420107585 CN200420107585 CN 200420107585 CN 200420107585 U CN200420107585 U CN 200420107585U CN 2775840 Y CN2775840 Y CN 2775840Y
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packaging structure
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赵军毅
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型涉及一种无侧引脚的芯片封装结构。传统封装结构中包括四方扁平和球栅阵列芯片封装技术。它们各自有优缺点。本实用新型提供的无侧引脚的芯片封装结构包括：芯片；芯片承载片，所述芯片固定在所述芯片承载片；引脚，所述芯片通过金线与所述引脚相连；塑封体，将所述芯片、所述芯片承载片、所述金线和所述引脚封装在一起，且所述引脚的下侧面暴露于外。本实用新型的封装结构兼具了传统的四方扁平芯片封装结构和球栅阵列芯片封装结构的优点。

Description

一种无侧引脚的芯片封装结构
技术领域
本实用新型涉及集成电路领域，具体地说，涉及集成电路的芯片封装技术，尤其涉及无侧引脚的芯片封装结构。
背景技术
芯片封装是集成电路制造中的工艺过程之一。传统上，封装技术包括四方扁平芯片封装结构和球栅阵列芯片封装结构。图1和图2分别示出了这两种传统的封装结构的示意图。如图1所示，图1是传统的四方扁平芯片封装结构的示意图。四方扁平芯片封装结构包括基片10、芯片11和引脚12。芯片11通过粘接剂固定在基片10上，芯片11上的电路通过金线13与引脚12电连接。塑封体14将基片10、芯片11、金线13和部分引脚12封装在一起，形成最终的集成电路。被封装在塑封体14中的引脚部分称为内引脚，暴露于塑封体14外的引脚称为外引脚。当把集成电路安装于电路板上时，外引脚与电路板电连接。这种四方扁平的封装结构由于有侧方的外引脚，因此，外形尺寸较大，安装时占用了很大的电路板面积，不利于缩小最终产品的体积。另外，在这种结构的封装工艺过程中，虽然一种引脚框架可用于多颗器件的封装，但对于不同大小的芯片，仍需要准备不同的模具。
如图2所示，图2是传统的球栅阵列芯片封装结构的示意图。球栅阵列芯片封装结构包括有基板20、芯片21和位于基板20下方的焊球22。芯片21通过粘接剂固定在基板20上，芯片21上的电路通过金线23与焊球22电连接。塑封体24将基片20和芯片21封装在一起，形成最终的集成电路。这种球珊阵列芯片封装结构无侧方的外引脚，因此，可以实现较小的封装尺寸。但由于这种封装结构工艺中，一种基板只能对应一颗芯片器件，增加了工艺过程中的模具成本。
实用新型内容
因此，本实用新型的目的在于提供一种无侧引脚的芯片封装结构，其兼具有四方扁平封装结构和球栅阵列封装结构的优点。
根据上述目的，本实用新型提供的无侧引脚的芯片封装结构包括：
芯片；
芯片承载片，所述芯片固定在所述芯片承载片；
引脚，所述芯片通过金线与所述引脚相连；
塑封体，将所述芯片、所述芯片承载片、所述金线和所述引脚封装在一起，且所述引脚的下侧面暴露于外。
在上述的芯片封装结构中，所述芯片通过粘接剂固定到所述芯片承载片上。
在上述的芯片封装结构中，所述引脚呈方形框架形式，围绕于所述芯片的四周。
下面将结合附图详细描述本实用新型的封装结构的一个实施例，本实用新型的上述和其它目的、结构和优点通过下面对实施例的详细描述将更为明了。
附图说明
图1是传统的四方扁平芯片封装结构的示意图；
图2是传统的球栅阵列芯片封装结构的示意图；
图3是本实用新型的无侧引脚的芯片封装结构的示意图；
图4是图3的俯视图。
具体实施方式
如图3所示，图3示出了本实用新型的无侧引脚的芯片封装结构的示意图。本实用新型的封装结构包括芯片1、芯片承载片2和引脚3。芯片1固定到芯片承载片2上，固定的方式可以与传统工艺相似，例如通过粘接剂固定。
引脚3采用方形框架形式。图4示出了图1的俯视图，为了显示出封装的内部结构，图4中没有画出塑封体4的结构。从图4中可以看出，结构为方框形式的引脚3围绕在芯片1的四周，并通过金线5将芯片1内的电路与引脚3电连接。
再回到参见图3，一塑封体4将芯片1、芯片承载片2、引脚3和金线5封装在一起，封装时，引脚3的下侧面暴露于外。引脚3暴露于外的部分可以与电路板的印刷线路相连。芯片承载片2可以如图所示部分暴露于外，也可以将芯片承载片2完全封装于塑封体4中。
如上所述，本实用新型的封装形式，单体以矩阵的形式连接在金属框架上，所以可以以矩阵的形式进行塑封，即可以采用阵列塑封工艺。又由于其金线的连接方式类似于四方扁平封装工艺，因此，针对不同的尺寸的封，可以共用主要的模具，节省了模具的费用。而且，由于可以采用金属框架，可以使用一种框架生产多颗器件。封装体的外侧面没有外引脚，其外引脚将置于封装体的底部，因此，大大降低了封装体的尺寸，使用时，少占电路板面积，有利于下游产品的小型化。

Claims (3)

1、一种无侧引脚的芯片封装结构包括：
芯片；
芯片承载片，所述芯片固定在所述芯片承载片；
其特征在于，还包括：
引脚，所述芯片通过金线与所述引脚相连；和
塑封体，将所述芯片、所述芯片承载片、所述金线和所述引脚封装在一起，且所述引脚的下侧面暴露于外。
2、如权利要求1所述的芯片封装结构，其特征在于，所述芯片通过粘接剂固定到所述芯片承载片上。
3、如权利要求1所述的芯片封装结构，其特征在于，所述引脚呈方形框架形式，围绕于所述芯片的四周。
CN 200420107585 2004-11-01 2004-11-01 一种无侧引脚的芯片封装结构 Expired - Lifetime CN2775840Y (zh)

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