CN2888649Y - 表面贴装式多晶片组合器件 - Google Patents

表面贴装式多晶片组合器件 Download PDF

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CN2888649Y
CN2888649Y CNU2006201024540U CN200620102454U CN2888649Y CN 2888649 Y CN2888649 Y CN 2888649Y CN U2006201024540 U CNU2006201024540 U CN U2006201024540U CN 200620102454 U CN200620102454 U CN 200620102454U CN 2888649 Y CN2888649 Y CN 2888649Y
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赵成钜
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

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Abstract

本实用新型涉及一种表面贴装式多晶片组合器件。本实用新型所要解决的技术问题是提供一种集成度高、封装体积小的表面贴装式多晶片组合器件，能够减小占用线路板的面积，同时降低因元器件过多而引起的相互干扰，提高可靠性。解决该问题的技术方案是：组合器件由两个三极管晶片T1、T2和四个金属引出脚封装而成，四个引脚中对角的两个引脚上各贴装有一个三极管晶片并引出三极管的一个极，其中一个三极管的另外两个极通过金属内引线分别与两个空引脚相连，另外一个三极管的余下两极中，一个极通过金属内引线与贴装有三极管晶片的引脚相连，另一极通过金属内引线跟与之不在同一侧的空引脚相连。本实用新型可用于各种电子线路中。

Description

表面贴装式多晶片组合器件
技术领域
本实用新型涉及半导体组合器件，特别是一种表面贴装式多晶片组合器件，适用于各种电子线路中。
背景技术
表面贴装半导体器件(SMD)由于其体积小，集成度高，被广泛的应用于电子通讯、计算机、电子仪器、彩电、充电器等产品。但是目前市场上大多是直接将单个三极管或二极管制成表面贴装式，虽然管子的体积减小了，但是元器件的数量并没有减少，所占据的电路板的面积还是比较大，也没有简化操作，已经越来越不能满足市场的需要了。
发明内容
本实用新型要解决的技术问题是：提供一种集成度高、封装体积小的表面贴装式多晶片组合器件，能够减小占用线路板的面积，同时降低因元器件过多而引起的相互干扰，提高可靠性。
本实用新型所采用的技术方案是：组合器件由两个三极管晶片T1、T2和四个金属引出脚封装而成，四个引脚中对角的两个引脚上各贴装有一个三极管晶片并引出三极管的一个极，其中一个三极管的另外两个极通过金属内引线分别与两个空引脚相连，另外一个三极管的余下两极中，一个极通过金属内引线与贴装有三极管晶片的引脚相连，另一极通过金属内引线跟与之不在同一侧的空引脚相连。
引脚I作为三极管T2的集电极C2与三极管T1的发射极E1的共同极并用金属内引线相连；引脚II作为三极管T2的基极B2；引脚III作为三极管T1的集电极C1；引脚IV作为三极管T1的基极B1与三极管T2的发射极E2的共同极并用金属内引线相连。
本实用新型的有益效果是：本实用新型在封装体内组合了多个晶片，提高了元器件的集成度，缩小了封装体积，并进一步减小线路板面积，可以简化操作、提高生产效率和可靠性、降低生产成本。
附图说明
图1是本实用新型的外形图。
图2是本实用新型的电原理图。
图3是本实用新型的内部结构图。
具体实施方式
如图1所示，本实施例具有四个金属引脚，采用国际通用的SOT-143封装形式，采用铁镍合金镀银框架，塑封成型后采用镀锡工艺，以确保引脚的可焊性，切筋打弯成型后的外形方便操作焊接。
如图2、图3所示，本例中封装块内有两个三极管晶片T1、T2，引脚I上用银浆烧结工艺贴装三极管T2，并作为三极管T2的集电极C2的引出脚，同时用金丝将三极管T2的集电极C2和三极管T1的发射极E1连接；引脚II作为三极管T2的基极B2的引出脚；用同样的方法在引脚III上贴装三极管T1，并作为三极管T1的集电极C1的引出脚；引脚IV通过金丝分别与三极管T1的基极B1和三极管T2的发射极E2相连。
本例只封装了两个三极管晶片，根据本实用新型的思路还可封装三个甚至多个三极管晶片，也可以是三极管和二极管的组合，总之引出脚是四个，管子与管子之间用金丝连接。

Claims (2)

1、一种表面贴装式多晶片组合器件，其特征在于：组合器件由两个三极管晶片(T1、T2)和四个金属引出脚封装而成，四个引脚中对角的两个引脚上各贴装有一个三极管晶片并引出三极管的一个极，其中一个三极管的另外两个极通过金属内引线分别与两个空引脚相连，另外一个三极管的余下两极中，一个极通过金属内引线与贴装有三极管晶片的引脚相连，另一极通过金属内引线跟与之不在同一侧的空引脚相连。
2、根据权利要求1所述的表面贴装式多晶片组合器件，其特征在于：引脚(I)作为三极管(T2)的集电极(C2)与三极管(T1)的发射极(E1)的共同极并用金属内引线相连；引脚(II)作为三极管(T2)的基极(B2)；引脚(III)作为三极管(T1)的集电极(C1)；引脚(IV)作为三极管(T1)的基极(B1)与三极管(T2)的发射极(E2)的共同极并用金属内引线相连。
CNU2006201024540U 2006-04-06 2006-04-06 表面贴装式多晶片组合器件 Expired - Fee Related CN2888649Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970412A (zh) * 2019-12-18 2020-04-07 深圳成光兴光电技术股份有限公司 一种光电接收二极管和三极管的集成封装结构以及电路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970412A (zh) * 2019-12-18 2020-04-07 深圳成光兴光电技术股份有限公司 一种光电接收二极管和三极管的集成封装结构以及电路

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Granted publication date: 20070411

Termination date: 20100406