CN2545707Y - 表面贴装式多晶片组合器件 - Google Patents

表面贴装式多晶片组合器件 Download PDF

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Publication number
CN2545707Y
CN2545707Y CN02234145U CN02234145U CN2545707Y CN 2545707 Y CN2545707 Y CN 2545707Y CN 02234145 U CN02234145 U CN 02234145U CN 02234145 U CN02234145 U CN 02234145U CN 2545707 Y CN2545707 Y CN 2545707Y
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wafer
diode
leading
triode
pole
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CN02234145U
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王建国
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Hangzhou Best Electric Co ltd
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Hangzhou Best Electric Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

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Abstract

本实用新型涉及表面贴装式多晶片组合器件。所要解决的技术问题是提供一种在同样的封装体积内元器件的集成度更高，电路更多样化，应用更灵活，焊接简便、工效高、可靠性强、生产成本低的表面贴装式多晶片组合器件。解决该问题的技术方案是：组合器件由两个二极管晶片和一个三极管晶片复合封装而成，四个引出脚中有二个引出脚上分别贴装有二极管晶片并引出二极管的一个极；另一个引出脚贴装三极管晶片并引出三极管的一个极；最后一个引出脚通过金属内引线与二个二极管的另一个极相连作为它们的共同极，三极管的另外二个极也通过金属内引线分别与两个贴有二极管晶片的引出脚相连。本实用新型可用于各种电子线路。

Description

表面贴装式多晶片组合器件
技术领域
本实用新型涉及半导体组合器件，尤其是一种表面贴装式多晶片组合器件。适用于各种电子线路。
背景技术
表面贴装技术(SMT)是当代电子整机制造业中采用最广泛的先进主流技术，而表面贴装技术的发展在很大程度上取决于表面贴装元器件(SMD)的发展速度，就目前国内市场上该类器件而言，还存在着体积较大、集成度低、电路品种少的不足。
发明内容
本实用新型要解决的技术问题是：提供一种在同样的封装体积内元器件的集成度更高，因而占据的面积更小，电路更多样化，应用更灵活，焊接简便、工效高、可靠性强、生产成本低的表面贴装式多晶片组合器件。
本实用新型所采用的技术方案是：表面贴装式多晶片组合器件，具有四个金属引出脚，其结构特点是组合器件由两个二极管晶片和一个三极管晶片复合封装而成，四个引出脚中有二个引出脚上分别贴装有二极管晶片并引出二极管的一个极；另一个引出脚贴装三极管晶片并引出三极管的一个极；最后一个引出脚通过金属内引线与二个二极管的另一个极相连作为它们的共同极，三极管的另外二个极也通过金属内引线分别与两个贴有二极管晶片的引出脚相连。
本实用新型的引出脚I、IV分别作为二极管K1、K2的阴极N1、N2，同时又是三极管T的发射极E和基极B，引出脚III作为三极管的集电极C，引出脚II作为两二极管K1、K2的共阳极并用金属内引线相连，三极管的发射极E和基极B也用金属内引线分别与引出脚I、IV相连。
本实用新型的有益效果是：在同样的封装体积内元器件的集成度更高，即反过来说对于相同的单元电路，可成倍或几倍地缩小封装体积，从而减小印制线路板的面积。本产品还可简化装机操作、提高工效，电路可根据需要灵活设计，应用范围广泛，可靠性强，生产成本低。
附图说明
图1是本实用新型的外型图。
图2是本实用新型的电原理图。
图3是本实用新型的结构连接图。
具体实施方式
如图所示，本实施例封装块有四个金属引出脚，封装块内有两个二极管晶片(本例为两个开关管K1、K2)和一个三极管晶片T。引出脚I上贴装开关管晶片K1并作为该开关管的阴极N1，同时该引出脚还是三极管T的发射极E；引出脚IV上贴装开关管晶片K2并作为该开关管的阴极N2，同时该引出脚还是三极管T的基极B；引出脚III上贴装三极管晶片T并作为该三极管的集电极C；开关管K1、K2的阳极用金属内引线相连后连接到引出脚II上；三极管晶片T的另外两个极E和B也分别通过金属内引线连接到引出脚I和IV上。

Claims (2)

1.一种表面贴装式多晶片组合器件，具有四个金属引出脚，其特征在于：组合器件由两个二极管晶片和一个三极管晶片复合封装而成，四个引出脚中有二个引出脚上分别贴装有二极管晶片(K1、K2)并引出二极管的一个极；另一个引出脚贴装三极管晶片(T)并引出三极管的一个极；最后一个引出脚通过金属内引线与二个二极管的另一个极相连作为它们的共同极，三极管的另外二个极也通过金属内引线分别与两个贴有二极管晶片的引出脚相连。
2.根据权利要求1所述的表面贴装式多晶片组合器件，其特征在于：引出脚(I、IV)分别作为二极管(K1、K2)的阴极(N1、N2)，同时又是三极管(T)的发射极(E)和基极(B)，引出脚(III)作为三极管的集电极(C)，引出脚(II)作为两二极管(K1、K2)的共阳极并用金属内引线相连，三极管的发射极(E)和基极(B)也用金属内引线分别与引出脚(I、IV)相连。
CN02234145U 2002-05-16 2002-05-16 表面贴装式多晶片组合器件 Expired - Fee Related CN2545707Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109509741A (zh) * 2017-09-15 2019-03-22 金龙联合汽车工业（苏州）有限公司 一种集成式二极管

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109509741A (zh) * 2017-09-15 2019-03-22 金龙联合汽车工业（苏州）有限公司 一种集成式二极管

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