CN1549341A - 由导线架建构的无管脚式半导体封装件及工序 - Google Patents
由导线架建构的无管脚式半导体封装件及工序 Download PDFInfo
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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Abstract
一种由导线架建构的无管脚式半导体封装件及工序,可用以制造一无管脚式的半导体封装件,例如四方形平面无管脚式封装件;其特点在于形成一凹穴在导线架的置晶部的置晶表面上,作为封装胶体的栓扣结构,借此将封装胶体栓扣于定位上不易发生脱层现象。此外,由于凹穴的形成可降低芯片的顶部高度,因此可增加封装胶体位于焊线上方的部分的厚度,借此避免焊线外露,使得整体的封装件的优良率更为提高。
Description
技术领域
本发明是关于一种半导体封装技术,特别是关于一种由导线架建构的无管脚式半导体封装技术,它可用来制造无管脚式的半导体封装件,例如四方形平面无管脚式(Quad Flat No-lead,QFN)封装件。
背景技术
四方形平面无管脚式(Quad Flat Non-leaded,QFN)半导体封装技术是半导体业界常用的一种芯片封装技术,特点在于其中的外接电性接触点没有设计成突出于外缘的管脚,而是设计成非突出式的底部焊垫,因此使得整体的封装尺寸更为轻薄短小。利用表面贴装技术(SurfaceMount Technology,SMT),即可将外露的底部焊垫焊接及电性藕接到外部的印刷电路板上。
相关的专利技术例如包括:美国专利第5,172,214号″LEADLESSSEMICONDUCTOR DEVIDE AND METHOD FOR MAKING THESAME″;美国专利第6,229,200号″SAW-SINGULATED LEADLESSPLASTIC CHIP CARRIER″;以及美国专利第6,143,981号″PLASTICINTEGRATED CIRCUIT PACKAGE AND METHOD ANDLEADFRAME FOR MAKING THE PACKAGE″;等等。
图1即显示根据美国专利第5,172,214号的专利技术建构的QFN封装件的剖面结构形态。如图所示,此QFN封装件至少包括:(a)一导线架110,具有一中央的置晶部111和一周边的管脚部(包括多支管脚)112;(b)一半导体芯片120,安置在导线架110的置晶部111上;(c)一组焊线130,例如是金线,用以将芯片120电性藕接至导线架110的管脚部112;以及(d)一封装胶体140,用以包覆芯片120和焊线130,但至少暴露出导线架110的管脚部112的底部表面,但也可同时暴露出导线架110的置晶部111的底部表面。
上述图1所示的QFN封装件的一个缺点在于,其中的封装胶体140常会由于导线架110与封装胶体140之间的热膨胀系数(Coefficient ofThermal Expansion,CTE)的差异而受到热应力的影响,产生脱层现象(delamination),也就是在封装胶体140与导线架110的置晶部111和管脚部112之间产生裂缝141、142,造成质量问题。
图2即显示上述问题的一种解决方法,它是根据美国专利第6,229,200和6,143,981号建构的封装结构。如图所示,此QFN封装件包括:(a)一导线架210,具有一中央的置晶部211和一周边的管脚部212;(b)一半导体芯片220,是安置在导线架210的置晶部211上;(c)一组焊线230,例如是金线,用以将芯片220电性藕接导线架210的管脚部212;以及(d)一封装胶体240,用以包覆该半导体芯片220和该组焊线230,但至少暴露出导线架210的管脚部212的底部表面,但也可同时暴露出导线架210的置晶部211的底部表面。此QFN封装件的特点是,在导线架210的置晶部211和管脚部212的底面上形成阶梯状结构部211a、212a、或将导线架210的表面粗糙化,借此增加封装胶体240与导线架210之间的附着力,防止封装胶体240发生脱层现象。
上述图2所示的QFN封装件的缺点在于,当需要将整体封装尺寸变薄(例如制作厚度小于0.5mm的封装件时)而将其中的导线架210进一步薄化时,导线架210上的阶梯状结构部211a、212a会因过薄而无法提供足够的附着力,使封装胶体240易于再产生脱层现象。举例来说,如图2所示,若整体封装尺寸为0.5mm时,导线架210的厚度为0.2mm、芯片220的厚度为0.15mm、焊线230的弧高为0.127mm,使得封装胶体240中位于焊线230上方的厚度仅为0.023mm,易于发生焊线外露出胶体的情况,造成产品不良。若将导线架210的厚度变薄至0.127mm,则其可增加封装胶体240中位于焊线230上方的厚度至0.096mm;但此时由于导线架210过薄(仅有0.127mm),因此导线架210上的阶梯状结构部211a、212a会因过薄而无法提供足够的附着力,使得封装胶体240仍易于产生脱层现象。
再有当芯片220是大尺寸的芯片时,较大的导线架210的置晶部211会产生较大的热应力,使得导线架210无法仅靠阶梯状结构部及粗糙化的表面提供足够的附着力,使封装胶体240易于产生脱层现象。
发明内容
为克服上述现有技术的缺点,本发明的主要目的在于提供一种新的半导体封装技术,可用来制作0.5mm以下的超薄型QFN封装件,不会使封装胶体产生脱层现象。
本发明的另一目的在于提供一种新的半导体封装技术,可用来封装大尺寸的芯片,不会使得封装胶体产生脱层现象。
本发明的又一目的在于提供一种新的半导体封装技术,能够在不减少导线架整体厚度的情况下,即可用来制作0.5mm以下的超薄型QFN封装件,且不会使封装胶体产生脱层现象。
本发明的由导线架建构的无管脚式半导体封装件至少包括:一导线架,具有一中央的置晶部和一周边的管脚部;其中该置晶部的一表面上形成有一预定深度的凹穴;至少一半导体芯片,是安置在该导线架的置晶部上的凹穴中;一组焊线,用以将该半导体芯片电性藕接至该导线架的管脚部;以及一封装胶体,用以包覆该半导体芯片和该焊线,但至少暴露出该导线架的管脚部的部分表面。
本发明的由导线架建构的无管脚式半导体封装工序至少包括:(1)预制一导线架,具有一中央的置晶部和一周边的管脚部;其中该置晶部的一表面上形成有一预定深度的凹穴;(2)进行一置晶程序,借以将至少一半导体芯片安置在该导线架的置晶部上的凹穴中;(3)进行一焊线程序,借以利用一组焊线将该半导体芯片电性藕接至该导线架的管脚部;以及(4)进行一封装胶体工序,借以形成一封装胶体,包覆该半导体芯片和该焊线,但至少暴露出该导线架的管脚部的部分表面。
利用本发明可制造一无管脚式的半导体封装件,例如四方形平面无管脚式(Quad Flat No-lead,QFN)封装件;其特点在于形成一凹穴在导线架的置晶部的置晶表面上,作为封装胶体的栓扣结构,借此将封装胶体栓扣于定位上,可用来封装大尺寸的芯片,还可制作0.5mm以下的超薄型QFN封装件,不易发生脱层现象。此外,由于凹穴的形成可降低芯片的顶部高度,因此可增加封装胶体位于焊线上方部分的厚度,借此避免焊线外露,使得整体的封装件的优良率提高。因此本发明较现有技术具有更佳的进步性及实用性。
附图说明
图1(现有技术)是一剖面结构示意图,显示一种现有的QFN封装件的剖面结构形态;
图2(现有技术)是一剖面结构示意图,显示另一种现有的QFN封装件的剖面结构形态;
图3A是一剖面结构示意图,显示本发明的无管脚式半导体封装技术采用的导线架的剖面结构形态;
图3B是一正面结构示意图,显示图3A所示的导线架的正面结构形态;
图3C是一剖面结构示意图,显示本发明的无管脚式半导体封装技术中的置晶程序;
图3D是一剖面结构示意图,显示本发明的无管脚式半导体封装技术中的焊线程序;
图3E是一剖面结构示意图,显示本发明的无管脚式半导体封装技术中的封装胶体工序。
具体实施方式
实施例
以下即配合图3A至图3E,详细说明本发明的无管脚式半导体封装技术的实施例。在以下实施例中,本发明的无管脚式半导体封装技术是例如用以制作一个四方形平面无管脚式(Quad Flat No-lead,QFN)封装件。
请首先同时参阅图3A的剖面图和图3B的上视图,本发明的无管脚式半导体封装技术在工序上的第一步骤是预制一导线架310,其具有一中央的置晶部311和一周边的管脚部(包括多条管脚)312。本发明的特点在于该导线架310的置晶部311的置晶表面上形成有一凹穴313,其形成方法例如是采用半蚀刻技术(half etch),将导线架310的置晶部311的上表面蚀刻至一预定的深度。举例来说,若该导线架310的整体厚度为0.2mm,则该凹穴313的预定深度可例如是0.1mm。此外,该导线架310的置晶部311和管脚部312可进而形成有阶梯状结构部311a、312a。
接着请参阅图3C,下一个步骤是进行一置晶程序,借以将至少一半导体芯片320以粘贴方式,安置在导线架310的置晶部311上的凹穴313中。此半导体芯片320的厚度例如是0.15mm。
接着请参阅图3D,下一个步骤是进行一焊线程序,借以利用一组焊线330,例如是金线,将该半导体芯片320电性藕接至导线架310的管脚部312。在此实施例中,该组焊线330的弧高(loop height)例如是0.127mm。
接着请参阅图3E,最后一个步骤是进行一封装胶体工序,借此形成一封装胶体340,用以包覆半导体芯片320和所有的焊线330,但至少要暴露出导线架310的管脚部312的底部表面,且也可同时暴露出导线架310的置晶部311的底部表面。这就完成了本发明的无管脚式半导体封装工序。
完成上述的QFN封装工序之后,由图3E可看出,导线架310的置晶部311上的凹穴313可作为封装胶体340的一个栓扣结构,借此将该封装胶体340栓扣于定位上而不易发生脱层现象。此外,由于该凹穴313的形成可降低芯片320的顶部高度,因此可增加封装胶体340位于焊线330上方部分的厚度。举例来说,如图3E所示,封装胶体340位于焊线330上方部分的厚度可增加至0.123mm,其大于图2所示的现有技术的0.023mm,从而避免焊线外露,因此提高整体的封装件的优良率。
总而言之,本发明提供了一种新颖的半导体封装技术,可制造一无管脚式的半导体封装件,例如为QFN封装件;且其特点在于形成一凹穴在导线架的置晶部的置晶表面上,用以作为封装胶体的栓扣结构,借此将封装胶体栓扣于定位上而不易发生脱层现象。此外,由于凹穴的形成可降低芯片的顶部高度,因此可增加封装胶体位于焊线上方部分的厚度,避免焊线外露,使整体的封装件的优良率更为提高。本发明因此较现有技术具有更佳的进步性及实用性。
Claims (9)
1.一种无管脚式半导体封装件,其特征在于,该封装件至少包括:
一导线架,具有一中央的置晶部和一周边的管脚部;其中该置晶部的一表面上形成有一预定深度的凹穴;
至少一半导体芯片,是安置在该导线架的置晶部上的凹穴中;
一组焊线,用以将该半导体芯片电性藕接至该导线架的管脚部;以及
一封装胶体,用以包覆该半导体芯片和该焊线,但至少暴露出该导线架的管脚部的部分表面。
2.如权利要求1所述的无管脚式半导体封装件,其特征在于,该导线架的置晶部上凹穴的形成方法是采用半蚀刻技术。
3.如权利要求1所述的无管脚式半导体封装件,其特征在于,这些焊线是金线。
4.如权利要求1所述的无管脚式半导体封装件,其特征在于,该导线架的置晶部和管脚部进而形成有阶梯状的结构部。
5.一种无管脚式半导体封装工序,其特征在于,该工序至少包括:
(1)预制一导线架,具有一中央的置晶部和一周边的管脚部;其中该置晶部的一表面上形成有一预定深度的凹穴;
(2)进行一置晶程序,借以将至少一半导体芯片安置在该导线架的置晶部上的凹穴中;
(3)进行一焊线程序,借以利用一组焊线将该半导体芯片电性藕接至该导线架的管脚部;以及
(4)进行一封装胶体工序,借以形成一封装胶体,包覆该半导体芯片和该焊线,但至少暴露出该导线架的管脚部的部分表面。
6.如权利要求5所述的无管脚式半导体封装工序,其特征在于,在步骤(1)中,该导线架的置晶部上凹穴的形成方法是采用半蚀刻技术。
7.如权利要求5所述的无管脚式半导体封装工序,其特征在于,在步骤(1)中,该导线架的置晶部和管脚部进而形成有阶梯状的结构部。
8.如权利要求5所述的无管脚式半导体封装工序,其特征在于,在步骤(3)中,是采用焊线技术借由一组焊线将该半导体芯片电性藕接至该导线架的管脚部。
9.如权利要求8所述的无管脚式半导体封装工序,其特征在于,这些焊线是金线。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101533818B (zh) * | 2008-03-12 | 2013-01-16 | 展晶科技(深圳)有限公司 | 集成电路元件的封装结构及其制造方法 |
CN103177974A (zh) * | 2011-12-23 | 2013-06-26 | 丽智电子(昆山)有限公司 | 铜片电极的离散式电子组件制造工艺 |
CN103928353A (zh) * | 2014-04-14 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | 无外引脚封装构造及其制造方法与导线框架 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101533818B (zh) * | 2008-03-12 | 2013-01-16 | 展晶科技(深圳)有限公司 | 集成电路元件的封装结构及其制造方法 |
CN103177974A (zh) * | 2011-12-23 | 2013-06-26 | 丽智电子(昆山)有限公司 | 铜片电极的离散式电子组件制造工艺 |
CN103177974B (zh) * | 2011-12-23 | 2014-10-29 | 丽智电子(昆山)有限公司 | 铜片电极的离散式电子组件制造工艺 |
CN103928353A (zh) * | 2014-04-14 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | 无外引脚封装构造及其制造方法与导线框架 |
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