TWI480993B - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

Info

Publication number
TWI480993B
TWI480993B TW099135788A TW99135788A TWI480993B TW I480993 B TWI480993 B TW I480993B TW 099135788 A TW099135788 A TW 099135788A TW 99135788 A TW99135788 A TW 99135788A TW I480993 B TWI480993 B TW I480993B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor device
lead frame
wafer
semiconductor
Prior art date
Application number
TW099135788A
Other languages
English (en)
Other versions
TW201135890A (en
Inventor
Motoharu Haga
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of TW201135890A publication Critical patent/TW201135890A/zh
Application granted granted Critical
Publication of TWI480993B publication Critical patent/TWI480993B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335—Material
    • H01L2224/33505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/1576—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Description

半導體裝置及半導體裝置之製造方法
本發明係關於一種半導體裝置及其製造方法。
先前，自環境負荷之觀點而言，要求降低半導體裝置中之鉛之使用量。
半導體裝置中，例如SOP(Small Outline Package，小尺寸封裝)、QFP(Quad Flat Package，方形扁平封裝)中之外部引線之外裝鍍敷、以及BGA(Ball Grid Array，球柵陣列)中之焊球等之類用於裝置外部之外部構成材係使用鉛。又，如封裝內部之半導體晶片與引線框架之間之接合材等之類用於裝置內部之內部構成材係使用鉛。
關於外部構成材，經替代材料之研究已基本達成使鉛之含量達到固定比率以下之無鉛化。相對於此，關於內部構成材，並不存在適於替代之材料。因此，使用例如Pb-xSn-yAg(x及y為正數)等含鉛之金屬。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利2007-67158號公報
Bi係易於與形成於半導體晶片及引線框架之相對於接合材之接合部分中之金屬層通常所含有之Au、Ag、Ni等金屬元素發生反應。Bi會與該等金屬元素形成化合物或形成 共晶組成。
因此，若Au、Ag、Ni等金屬元素暴露於金屬層之最表面，則使用Bi作為接合材時，由於Bi與上述金屬元素接觸，故於接合材之與金屬層之界面附近有時會形成Bi與上述金屬元素之合金層(金屬間化合物)。又，存在接合材整體成為Bi與上述金屬元素之共晶組成之情形。
Bi與上述金屬元素之金屬間化合物硬而脆，故於半導體裝置之溫度循環試驗(TCY試驗)時，存在該金屬間化合物成為破壞起因之虞。
又，Bi與上述金屬元素之共晶組成物之熔點低於Bi單體之熔點。例如，Bi單體之熔點約為271℃，相對於此，Bi與Au之共晶組成物之熔點約為241℃，Bi與Ag之共晶組成物之熔點約為262℃。因此，於安裝半導體裝置時若進行回焊(峰值溫度約為260℃)，則存在接合材再熔融之虞。
本發明之目的在於提供一種可藉由於半導體晶片與引線框架之間之接合層中使用Bi系材料而達成無鉛化，進而可提高接合層之耐溫度循環性且可較高地維持接合層之熔點之半導體裝置及其製造方法。
用以達成上述目的之本發明之半導體裝置係包含：晶片焊墊，其表面含有Cu；半導體晶片，其包含形成背面之Cu層，且配置成與上述晶片焊墊之上述表面對向；及接合層，其位於上述晶片焊墊與上述半導體晶片之間；且，上述接合層係包含Bi系材料層、及相對於該Bi系材料層自上 述晶片焊墊與上述半導體晶片之對向方向之兩側夾住上述Bi系材料層之不含Pb之Cu合金層。
根據該構成，將晶片焊墊與半導體晶片接合之接合層係含有不含Pb之Cu合金及Bi系材料，故可達成接合層之無鉛化。
又接合層之Bi系材料層係由不含Pb之Cu合金層自晶片焊墊與半導體晶片之對向方向之兩側夾住，故與該等合金層相接觸。
Bi系材料層雖與Cu合金層接觸，但Cu幾乎不與Bi發生反應，故幾乎不存在由於該等層彼此接觸而導致接合層之熔點降低或耐溫度循環性降低之虞。
又於晶片焊墊或半導體晶片上，即便形成有包含存在使Bi系材料層之特性降低之虞之Au、Ag、Ni等抑制性金屬元素之金屬層，亦可藉由上述Cu合金層而防止Bi系材料層與上述金屬層接觸。其結果可防止Bi與上述抑制性金屬元素之金屬間化合物之形成、及Bi與上述抑制性金屬元素之共晶組成物之形成。由此，可提高接合層之耐溫度循環性，且可較高地維持接合層之熔點。
上述半導體裝置可藉由例如本發明之半導體裝置之製造方法而製造。即，可藉由包含下述步驟之半導體裝置之製造方法而製造：準備於背面包含Cu層之半導體晶片；以經由接合材且使上述Cu層與上述接合材接觸之方式，使上述半導體晶片接合於表面含有Cu之晶片焊墊上，該接合材含有：不含Cu及Ph之異種金屬、及Bi系材料；及於上述半導 體晶片接合後，對上述晶片焊墊進行熱處理。
根據該方法，以使半導體晶片之Cu層與接合材接觸之方式，將半導體晶片接合於晶片焊墊，其後對晶片焊墊進行熱處理。藉此，半導體晶片之Cu層及形成晶片焊墊之表面之Cu分別與接合材中之異種金屬(不含Cu及Pb之金屬)發生反應，從而於Cu層及晶片焊墊之表面附近形成Cu合金層。另一方面，關於接合材中之異種金屬以外之成分，由於幾乎不與Cu發生反應，故作為由合金層夾持之Bi系材料層殘存於合金層之間。
於形成接合層時，接合材中之成分(Bi系材料及異種金屬)並未與Cu以外之金屬元素接觸，進而，於晶片焊墊與半導體晶片之對向方向之Bi系材料層之兩側形成有合金層。因此，於晶片焊墊或半導體晶片上即便形成有包含Au、Ag、Ni等抑制性金屬元素之金屬層，亦可防止Bi系材料層與上述抑制性金屬元素接觸。
而且，作為接合材中之異種金屬，含有Sn之情形時，Cu合金層之至少一層可形成為Cu-Sn合金層。又，作為接合材中之異種金屬，含有Zn之情形時，Cu合金層之至少一層可形成為Cu-Zn合金層。
此種Cu-Sn合金及Cu-Zn合金均為高強度之金屬，而並非如Bi-Au合金、Bi-Ag合金等硬而脆之金屬。因此，可藉由該等合金層而使半導體晶片及晶片焊墊與接合層之接合強度提高。
又，當上述半導體晶片包含背面側形成有上述Cu層之Si 基板之情形時，較佳為於上述Si基板與上述Cu層之間形成有可對Si半導體歐姆接觸之金屬層。藉此，便可經由該金屬層而而使Cu層與Si基板導通。其結果可電性連接Si基板與晶片焊墊。
而且，此種態樣之半導體裝置例如可藉由於上述本發明的半導體裝置之製造方法之準備上述半導體晶片之步驟中執行下述步驟而製造：於上述Si基板之背面形成可對Si半導體歐姆接觸之金屬層；及於該金屬層上形成上述Cu層。
又，本發明之半導體裝置中，上述晶片焊墊亦可配合配置於其周圍之引線，構成引線框架。亦即，晶片焊墊可為引線框架之一部分。
又，當本發明之半導體裝置係具有樹脂封裝之樹脂密封型半導體裝置之情形時，較佳為，使上述引線框架之背面成為自上述樹脂封裝中露出之露出面，且上述引線框架之表面由上述樹脂封裝進行密封，並且上述引線框架之上述晶片焊墊及/或上述引線包含：變形部，其係以藉由自上述密封面側按壓上述密封面之周緣部而使上述密封面變形之方式形成；及突出部，其係形成於上述變形部之側方，且於上述樹脂封裝內自其側面突出。
根據該構成，於將引線框架之側面密封之樹脂封裝內，突出部自引線框架之側面突出，並且該突出部陷入樹脂封裝中。因此，於密封面(引線框架之表面)與露出面(引線框架之背面)之對向方向上，當對引線框架受到朝向封裝下表面側(引線框架之露出面側)之力時，會卡住陷入樹脂封 裝中之突出部。其結果可抑制引線框架之脫落。
又，引線框架之密封面係其整個區域並非同一平面，於其周緣部具有變形部。因此，根據變形部之形狀，於與密封面和露出面之對向方向交叉之橫方向上，若引線框架受力，則密封面之周緣部成為相對該橫向力之阻力。其結果，與引線框架之密封面之整個區域為同一平面之情形相比，可抑制引線框架之橫移。
即，根據該構成，可提供一種能夠防止引線框架自樹脂封裝中脫落且能抑制引線框架橫移之半導體裝置。
上述變形部可為藉由上述密封面朝向上述引線框架之厚度方向凹陷而形成之凹部。於該情形時，由於密封面上形成有凹部，故藉由樹脂封裝進入至凹部內，而使樹脂封裝之一部分嵌合於凹部。因此，當引線框架受到上述橫向力時，凹部會被凹部內之樹脂封裝卡住。其結果可防止引線框架之橫移。
又，較佳為，上述密封面之上述凹部之周邊部呈隆起狀。該情形時，由於凹部之周邊部隆起，故於上述對向方向上，密封面之一部分鼓起。因此，當引線框架受到上述橫向力時，該鼓起之部分成為對於橫移之阻力。其結果可更確實防止引線框架之橫移。
又，較佳為，於上述凹部內形成有突起。該情形時，由於凹部內形成有突起，故於凹部內之樹脂封裝內突起呈突出狀。可藉由該突起，而於凹部內使引線框架陷入樹脂封裝。因此，可使凹部與樹脂封裝之嵌合結構複雜。其結果 可使樹脂封裝對於凹部之嵌合強度提高。
又，上述引線框架亦可含有Cu。該情形時，引線框架之表面可為未由鍍敷或濺鍍等處理之金屬層被覆之非被覆面。亦即，構成引線框架之Cu亦可露出於引線框架之整個表面。藉此，於製造半導體裝置時，無需對引線框架進行鍍敷或濺鍍等處理，故可降低成本。
又，於含有Cu之引線框架上，裝載有半導體晶片之晶片焊墊可具有朝向其表面側依序積層之包含不含Cu之金屬層與引線框架側Cu層的積層構造。
作為金屬層，可舉出例如Ag層、Au層、Ni層等。該情形時，配置於晶片焊墊之周圍之複數條引線，較佳為於引線之最表面露出有金屬層。可藉由適當選擇金屬層之種類而將Au線、Cu線等各種金屬線用作與引線連接之接線。
又，於本發明之半導體裝置之製造方法中，接合上述半導體晶片之步驟亦可包含下述步驟：將上述半導體晶片接合於包含上述晶片焊墊、及配置於該晶片焊墊周圍之複數條引線之引線框架的上述晶片焊墊。
該情形時，本發明之半導體裝置之製造方法亦可進而包含下述步驟：於接合上述半導體晶片之步驟之前執行，自上述引線框架之上述晶片焊墊及/或上述引線之表面側，利用打線接合機之毛細管或與上述毛細管交換而安裝於上述打線接合機上之沖壓成形工具，按壓上述表面之周緣部，使上述表面變形，藉此形成變形部及自上述引線框架之側面突出之突出部；及於上述引線框架之熱處理後，以 使上述引線框架之上述背面露出之方式，藉由樹脂封裝來密封上述引線框架之上述表面側。
根據該方法，藉由利用沖壓成形工具按壓引線框架表面之周緣部，而形成變形部及突出部。因此，即便引線框架之背面(自樹脂封裝露出之面)被覆蓋而難以自背面側進行蝕刻加工之情形時，亦可確實形成用以抑制引線框架脫落之突出部(防脫落結構)。又，由於利用打線接合機之毛細管或與毛細管交換而安裝於打線接合機上之沖壓成形工具按壓引線框架，故可將焦點集中於引線框架之周緣部，從而簡單且精密地使引線框架變形。
即，根據該構成，可提供一種即便於難以利用蝕刻於引線框架上形成防脫落結構之情形時，亦可簡單且精密地形成該防脫落結構之半導體裝置之製造方法。
又，於本發明之半導體裝置中，亦可於上述半導體晶片之表面形成電極焊墊。該情形時，上述電極焊墊可含有包含Al之金屬材料。
又，於本發明之半導體裝置中，形成於上述Si基板與上述Cu層之間之上述金屬層亦可為Au層。該情形時，本發明之半導體裝置較佳為更包含形成於上述Si基板與上述Au層之間之Ni層。又，Si基板之厚度可為220μm~240μm。
又，於本發明之半導體裝置中，較佳為，上述引線框架藉由鍍敷法而形成。該情形時，引線框架之厚度可為10μm~50μm。
又，本發明之半導體裝置中，上述晶片焊墊係俯視為四 角形，且上述複數條引線可以包圍該晶片焊墊之四周之方式配置。即，本發明之半導體裝置可為應用有QFN(Quad Flat Non-leaded，四邊形扁平無引腳)之半導體裝置。
該情形時，較佳為上述晶片焊墊係俯視時為大於上述半導體晶片之四角形，且上述晶片焊墊之上述密封面之上述周緣部包圍上述半導體晶片。
又，於本發明之半導體裝置中，上述Bi系材料層之厚度與上述Cu合金層之厚度之和即上述接合層之總厚度可為12μm~36μm。又，上述Bi系材料層之厚度可為10μm~30μm。又，上述Cu合金層之厚度可為1μm~3μm。
以下，參照隨附圖式詳細說明本發明之實施形態。
<第1實施形態>
圖1係本發明第1實施形態之半導體裝置之模式平面圖。圖2係本發明第1實施形態之半導體裝置之模式剖面圖，且表示圖1之A-A截斷面之剖面。圖3係圖2之由虛線圓B所包圍之部分之主要部分放大圖。圖4係圖2之由虛線圓C所包圍之部分之主要部分放大圖。圖5係圖2之由虛線圓D所包圍之部分之主要部分放大圖。再者，圖1表示樹脂封裝卸除後之狀態。
半導體裝置1係應用有QFN(Quad Flat Non-leaded)之半導體裝置。半導體裝置1具備：具有表面21及背面22之半導體晶片2；裝載有半導體晶片2之晶片焊墊3；配置於晶片焊墊3周圍之複數條電極引線4；將半導體晶片2與電極 引線4電性連接之接線5；及密封該等之樹脂封裝6。
半導體晶片2係具備俯視為四角形(例如，2.3mm×2.3mm左右四邊形)之Si基板7。Si基板7之厚度例如為220μm~240μm(較佳為230μm左右)。於Si基板7之上表面，形成有介隔層間絕緣膜將複數層佈線層積層所得之多層佈線結構(未圖示)，該多層佈線結構之最表面係由表面保護膜(未圖示)覆蓋。
於該表面保護膜上，形成有複數層用以使多層佈線結構之最上層佈線層露出之焊墊開口8。焊墊開口8係俯視為四角形，且於半導體晶片2之各邊緣分別設置有相同數量(圖1中，分別為4個)。各焊墊開口8係沿半導體晶片2之各邊等間隔配置。而且，佈線層之一部分係作為半導體晶片2之電極焊墊9而自各焊墊開口8露出。再者，形成有焊墊開口8之面形成半導體晶片2之表面21。
作為電極焊墊9而露出之最上層佈線層係含有例如包含Al(鋁)之金屬材料，具體而言，含有以Al為主成分之金屬材料(例如Al-Cu合金等)。
另一方面，於Si基板7之下表面(相對晶片焊墊3之對向面)上，形成有背金屬層10。該背金屬層10形成半導體晶片2之背面22。
如圖3所示，背金屬層10係具有自Si基板7之側依序積層有Au層11、Ni層12及Cu層13之3層結構。Au層11係可對Si半導體進行歐姆接觸，且與Si基板7之下表面接觸。Ni層12係相較成為背金屬層10之最表面之Cu層13形成於Si基板 7側，且用以防止Si基板7中之Si於背金屬層10之最表面析出之Si結核之層。
晶片焊墊3及複數條電極引線4係作為含有相同金屬薄板之引線框架14而形成。引線框架14係藉由例如鍍敷法而形成。作為用於鍍敷生長之金屬材料，可舉出例如主要含有Cu之Cu系素材，具體而言純度為99.9999%(6N)以上、純度為99.99%(4N)以上之高純度銅、Cu與異種金屬之合金(例如，Cu-Fe-P合金等)等；以及例如42合金(Fe-42% Ni)等之Fe系素材等。又，引線框架14之厚度例如為未達100μm，較佳為10μm~50μm。
晶片焊墊3係俯視大於半導體晶片2之四角形(例如，俯視為2.7mm見方左右)，且四角形環狀之周緣部33包圍半導體晶片2。
晶片焊墊3之表面31(由樹脂封裝6密封之密封面)係為未由鍍敷或濺鍍等處理之金屬薄膜被覆之非被覆面，且構成引線框架14之Cu系素材露出於整個表面31。
如圖4所示，於晶片焊墊3之周緣部33上，形成有複數個由晶片焊墊3之表面31朝向引線框架14之厚度方向凹陷而成之微小之接腳凹部34(變形部)。
該晶片焊墊3側之接腳凹部34係於周緣部33之各直線部分別設置有相同數量(圖1中，分別為6個)。各接腳凹部34係沿周緣部33之各邊等間隔配置。各接腳凹部34呈現朝向深度方向直徑變窄之錐形之剖面視圖近似碗狀，且具有例如10μm~50μm之最大直徑、5μm~25μm之深度。於晶片 焊墊3之表面31上，包圍各接腳凹部34之俯視圓環狀之周邊面35係於表面31相對裝載有半導體晶片2之裝載面36而隆起。裝載面36係相對晶片焊墊3之背面32(對佈線基板之安裝面)平行之面。
又，於晶片焊墊3之側面37上，在與周緣部33之各接腳凹部34對向之各位置處，形成有於與引線框架14之厚度方向正交之方向上突出之防脫落部38(突出部)。各防脫落部38形成於引線框架14之厚度方向上側，且剖面視圖中與各接腳凹部34鄰接。
而且，半導體晶片2及晶片焊墊3係藉由於Si基板7之下表面(半導體晶片2之背面22)及晶片焊墊3之表面31(裝載面36)作為接合面而相互對向之狀態下，使接合層15介於背面22與表面31之間而相互接合。由此，半導體晶片2以表面21朝向上方之姿勢由晶片焊墊3支持。
如圖3所示，接合層15係具備作為相對較厚之主層之Bi系材料層16；及作為相對較薄之副層之Cu-Sn合金層17、18。
Bi系材料層16中，可含有Bi作為主成分，且可含有不會對Bi之物性造成影響之程度之量的Sn、Zn、Co等作為副成分。
Cu-Sn合金層17、18中，含有Cu、與不含Cu及Pd之異種金屬即Sn之合金，且含有Cu作為主成分。
半導體晶片2側之Cu-Sn合金層17係於接合層15之與背金屬層10之Cu層13之界面附近以遍及其整個區域之方式形 成。藉此，Cu-Sn合金層17與背金屬層10之Cu層13接觸。Cu-Sn合金層17例如於晶片焊墊3與半導體晶片2之對向方向上，自Bi系材料層16之側朝向半導體晶片2側，具有由Cu6Sn5/Cu3Sn表示之積層構造。
另一方面，晶片焊墊3側之Cu-Sn合金層18係於接合層15之與晶片焊墊3之表面31之界面附近以遍及其整個區域之方式形成。藉此，Cu-Sn合金層18與晶片焊墊3之表面31接觸。Cu-Sn合金層18例如於晶片焊墊3與半導體晶片2之對向方向上，自Bi系材料層16之側朝向晶片焊墊3側，具有由Cu6Sn5/Cu3Sn表示之積層構造。
再者，Cu-Sn合金層17、18亦可於接合層15之與晶片焊墊3之表面31之界面附近、及接合層15之與背金屬層10之Cu層13之界面附近分別局部地形成。
而且，Bi系材料層16及Cu-Sn合金層17、18係呈現為於晶片焊墊3之表面31與背金屬層10之Cu層13之間，自晶片焊墊3與半導體晶片2之對向方向之兩側，由Cu-Sn合金層17、18夾住Bi系材料層16之3層結構(Cu-Sn合金層17/Bi系材料層16/Cu-Sn合金層18)。
上述接合層15之熔點例如為260℃~265℃，較佳為265℃~271℃。又，於半導體晶片2與晶片焊墊3接合之狀態下，接合層15之總厚度T(Bi系材料層16之厚度與Cu-Sn合金層17、18之厚度之和)例如為12μm~36μm。關於各層之厚度，例如，Bi系材料層16之厚度為10μm~30μm，Cu-Sn合金層17、18之厚度為1μm~3μm。
晶片焊墊3之背面32(對佈線基板之安裝面)係自樹脂封裝6中露出。於該露出之背面32上，形成有例如含有錫(Sn)、錫-銀合金(Sn-Ag)等金屬材料之晶片焊墊背面鍍敷層19。
如圖1所示，電極引線4係藉由設置於與晶片焊墊3之各側面37正交之各方向之兩側而配置於晶片焊墊3之周圍。與晶片焊墊3之各側面37對向之電極引線4係等間隔地配置於與該對向之側面37平行之方向上。各電極引線4係以長條之俯視長方形狀形成於與晶片焊墊3之側面37正交之方向(與晶片焊墊3對向之方向)上，且該對向方向上之長度(背面42側之長度)例如為450μm左右。
如圖5所示，電極引線4之表面41(接線5之連接面)係為未由鍍敷或濺鍍等處理之金屬薄膜被覆之非被覆面，且構成引線框架14之Cu系素材形成整個表面41。
於各電極引線4之晶片焊墊3側之緣部43上，形成有複數個由電極引線4之表面41(由樹脂封裝6密封之密封面)朝向引線框架14之厚度方向凹陷而成之微小之接腳凹部44(變形部)。
該電極引線4側之接腳凹部44呈現出朝向深度方向直徑變窄之剖面視圖近似碗狀，且具有例如10μm~50μm之最大直徑、5μm~25μm之深度。於電極引線4之表面41上，包圍各接腳凹部44之俯視圓環狀之周邊面45係於表面41相對於連接有接線5之連接面46而隆起。連接面46係相對電極引線4之背面42(對佈線基板之安裝面)平行之面。
又，於電極引線4之側面47上，以俯視時包圍緣部43之接腳凹部44之方式，形成有於與引線框架14之厚度方向正交之方向上突出之防脫落部48(突出部)。各防脫落部48係形成於引線框架14之厚度方向上側，且於剖面視圖中與接腳凹部44鄰接。
電極引線4之背面42(對佈線基板之安裝面)係自樹脂封裝6露出。於該露出之背面42上，形成有例如含有錫(Sn)、錫-銀合金(Sn-Ag)等金屬材料之引線背面鍍敷層20。
接線5係含有例如銅(例如，純度為99.9999%(6N)以上、純度為99.99%(4N)以上之高純度銅等，且有時含微量之雜質)。接線5係1對1地將一個電極焊墊9與一條電極引線4連接。
樹脂封裝6係呈現半導體裝置1之外形，且形成為近似長方體狀。關於樹脂封裝6之大小，其平面尺寸例如為4mm見方左右，其厚度例如為0.85mm左右。此種樹脂封裝6係含有例如環氧樹脂等公知之成型樹脂，且以覆蓋引線框架14之各表面31、41及各側面37、47並使各背面32、33露出之方式，密封半導體晶片2、接線5及引線框架14。樹脂封裝6係於晶片焊墊3之周緣部33及各電極引線4之緣部43分別進入至接腳凹部34及接腳凹部44內。
圖6A~圖6G係按照步驟順序表示圖1及圖2所示之半導體裝置之製造步驟之模式剖面圖。
為製造上述半導體裝置1，而例如圖6A所示，利用鍍敷 法於不鏽鋼基板23上，使引線框架14之材料以具備複數個包含晶片焊墊3及電極引線4之單元之圖案進行生長，藉此形成引線框架14。再者，圖6A~圖6G係將引線框架14之整體圖省略，而僅表示裝載1個半導體晶片2所需之1個單元量之晶片焊墊3及電極引線4。
其次，如圖6B所示，利用沖壓成形工具24，相對表面41垂直地撞擊電極引線4之晶片焊墊3側之緣部43。該沖壓成形工具24係與毛細管交換而安裝於下述用於打線接合之打線接合機者。因沖壓成形工具24之撞擊而於電極引線4之緣部43，作為沖壓成形工具24之凹痕而形成電極引線4側之接腳凹部44。又，形成接腳凹部44之同時，藉由利用沖壓成形工具24將電極引線4之接腳凹部44之周邊部分擴張，而使包圍接腳凹部44之電極引線4之周邊面45隆起，並且使防脫落部48自與接腳凹部44鄰接之電極引線4之側面47上突出。
再者，由沖壓成形工具24對電極引線4所施加之荷重係因作為目標之接腳凹部44之深度不同而不同，例如為200g~400g左右。又，作為沖壓成形工具24，可應用例如不具有穿透金屬線等之孔之沖壓毛細管(例如，TOTO公司製等)等。
其後，如圖6C所示，對剩餘之電極引線4亦進行與圖6B相同之步驟，藉此於所有電極引線4之緣部43形成接腳凹部44。
其次，如圖6C所示，以與圖6B相同之步驟，對晶片焊 墊3之周緣部33，利用沖壓成形工具24沿其各邊依序進行撞擊。藉此，形成晶片焊墊3側之接腳凹部34，且使包圍接腳凹部34之晶片焊墊3之周邊面35隆起，並且使防脫落部38自與接腳凹部34鄰接之晶片焊墊3之側面37突出。
另一方面，如圖6D所示，藉由於Si基板7之下表面依序積層Au層11、Ni層12及Cu層13而形成背金屬層10。由此，準備具有背金屬層10之半導體晶片2。
其次，如圖6E所示，將作為含有含Sn之Bi系材料之接合材之接合膏25塗佈於晶片焊墊3之表面31上。
接合膏25中Sn之含量較佳為例如總量可擴散至背金屬層10之Cu層13及晶片焊墊3之表面31之Cu之量，例如為4wt%以下，較佳為1~3wt%，更佳為1.5~2.5wt%。
於塗佈接合膏25之後，如圖6F所示，以背金屬層10之Cu層13與接合膏25接觸之方式，藉由半導體晶片2及晶片焊墊3夾住接合膏25。繼而，例如以290℃~300℃進行回焊(熱處理)。
藉此，如圖6G所示，背金屬層10之Cu層13及晶片焊墊3之表面31之Cu分別與接合膏25中之Sn發生反應，從而於Cu層13及表面31附近形成Cu-Sn合金層17、18。另一方面，接合膏25中之Bi幾乎未與Cu發生反應，故作為由該等夾持之Bi系材料層16而殘存於Cu-Sn合金層17、18之間。
其後，藉由接線5而連接所有半導體晶片2之各電極焊墊9與對應於各電極焊墊9之電極引線4。
於所有打線接合結束後，將引線框架14放置於成形模具 中，藉由樹脂封裝6而將所有半導體晶片2與引線框架14一併成批密封。
於樹脂封裝6進行密封後，將不鏽鋼基板23與引線框架14剝離。其次，於自樹脂封裝6露出之晶片焊墊3之背面32上形成晶片焊墊背面鍍敷層19，同時，於電極引線4之背面42上形成引線背面鍍敷層20。最後，使用切割機將引線框架14與樹脂封裝6一併截斷成各半導體裝置1之尺寸，藉此獲得圖1所示之半導體裝置1之單片。
如上所述，根據上述方法，塗佈於晶片焊墊3之表面31上之接合膏25以與背金屬層10之Cu層13接觸之方式，由半導體晶片2及晶片焊墊3夾住。其後，藉由實施回焊(熱處理)而形成具有Bi系材料層16及Cu-Sn合金層17、18之接合層15。
於形成接合層15時，接合膏25中之成分(Bi系材料及Sn)不會與Cu以外之金屬元素接觸，進而，於半導體晶片2與晶片焊墊3之對向方向上，於Bi系材料層16之兩側形成Cu-Sn合金層17、18。
因此，可防止存在使Bi系材料層16之特性下降之虞的背金屬層10之Au層11中之Au或Ni層12中之Ni等抑制性金屬元素與Bi系材料層16之接觸。其結果，可防止Bi與上述抑制性金屬元素之金屬間化合物之形成及Bi與上述抑制性金屬元素之共晶組成物之形成。由此，可提高接合層15之耐溫度循環性，且可較高地維持接合層15之熔點。
另一方面，Bi系材料層16雖與Cu-Sn層17、18接觸，但 Cu幾乎不與Bi發生反應，故幾乎不存在因該等層彼此接觸而導致接合層15之熔點降低或耐溫度循環性降低之虞。
又，由於接合層15含有Bi系材料層16及Cu-Sn合金層17、18，故可達成接合層15之無鉛化。
又，Cu-Sn合金係為高強度之金屬，而並非如Bi-Au合金、Bi-Ag合金等之硬而脆的金屬。因此，可藉由Cu-Sn合金層17、18，而使半導體晶片2及引線框架14與接合層15之接合強度提高。
又，於Si基板7之下表面接觸有Au層11，故可經由該Au層11而使Cu層13與Si基板7導通。藉此，可將Si基板7與晶片焊墊3電性連接。
又，晶片焊墊3之表面31及電極引線4之表面41均為未由鍍敷或濺鍍等處理之金屬薄膜被覆之非被覆面，故於製造半導體裝置1時，無需對引線框架14進行鍍敷或濺鍍等處理，故可降低成本。
又，根據本實施形態之半導體裝置1之構成，可解決下述課題。
所謂該課題，先前，為了將半導體裝置高密度地安裝於佈線基板上，而使用一種排除引線自樹脂封裝延伸，使引線框架之引線端子(與半導體晶片電性連接之端子部分)露出於封裝下表面從而可對佈線基板進行表面安裝之高密度安裝用之封裝。作為此種高密度安裝用之封裝，已知例如QFN(Quad Flat Non-leaded Package，四邊形扁平無引腳封裝)或SON(Small Outlined Non-leaded Package，小尺寸無 引腳封裝)等無引腳封裝。
於此種半導體封裝中，進而，於封裝下表面使引線框架之晶片焊墊(裝載有半導體晶片之支持部)露出之結構之封裝(例如，HQFN：Heat sinked Quad Flat Non-leaded Package，帶散熱器之扁平無引腳封裝)亦得以實用化，以提高來自半導體晶片之散熱性。
該等形態之封裝係使利用成型樹脂封裝之引線框架之安裝面與半導體晶片一併露出於封裝下表面之構成。因此，存在引線端子及晶片焊墊容易自封裝中脫落之不良情況。例如，於封裝安裝後之基板彎曲試驗等中，封裝受到外力時存在引線端子或晶片焊墊脫落之虞。
因此，使引線端子或晶片焊墊之剖面形狀為近似倒錐形，藉此使成型樹脂陷入該等側面中，從而設法防止引線端子或晶片焊墊之脫落。
上述剖面形狀係藉由例如於半導體晶片及引線框架進行封裝之前，自安裝面側(背面側)對引線框架進行蝕刻，去除引線端子或晶片焊墊之側面之一部分而形成。
作為引線框架，一直以來使用100μm~200μm左右之金屬薄板，但近年來，開始不斷使用藉由鍍敷法而形成之引線框架。例如正在研究藉由於基板上進行特定之引線框架圖案之鍍敷生長而形成引線框架之方法。此種方法可精密地控制引線框架之厚度，故或許可藉由較薄地形成引線框架而實現封裝之薄型化。
然而，引線框架與基板之剝離之時間係於引線框架與半 導體晶片一併封裝之後。因此，於封裝之前，由於引線框架(引線端子及晶片焊墊)之安裝面由基板所覆蓋，故難以自安裝面側對引線框架進行蝕刻加工。另一方面，於封裝後，即便將基板剝離，亦由於引線框架之側面已由成型樹脂覆蓋，而難以對側面進行蝕刻加工。
根據上述原因，於藉由鍍敷法而形成引線框架之情形時，存在難以形成引線框架之防脫落結構之不良情況。
又，關於先前之引線框架係與安裝面為相反側之密封面整個區域為同一平面，且以平面狀接觸於成型樹脂，故亦存在引線框架相對成型樹脂容易橫移之不良情況。
因此，本實施形態中，晶片焊墊3之側面37及電極引線4之側面47分別藉由樹脂封裝6而密封，且於密封側面37、47之樹脂封裝6內，晶片焊墊3側之防脫落部38自側面37突出，電極引線4側之防脫落部48自側面47突出。
該等防脫落部38、48於與引線框架14之厚度方向交叉之橫方向上，陷入樹脂封裝6中。因此，於引線框架14之厚度方向上，當引線框架14受到朝向樹脂封裝6之下表面側(引線框架14之露出面側)之力時，會卡住陷入樹脂封裝6中之防脫落部38、48。其結果可抑制引線框架14之脫落。
又，晶片焊墊3之表面31係整個區域並非同一平面，且於其周緣部33上形成有接腳凹部34，樹脂封裝6進入至接腳凹部34內。藉此，使樹脂封裝6之一部分嵌合於接腳凹部34。又，與晶片焊墊3之表面31相同，電極引線4之表面41係整個區域並非同一平面，且於其緣部43上形成有接腳 凹部44，樹脂封裝6進入至接腳凹部44內。藉此，使樹脂封裝6之一部分嵌合於接腳凹部44。
因此，於上述橫方向上引線框架14受力時，接腳凹部34、44內之樹脂封裝6會卡住接腳凹部34、44。其結果可防止引線框架14之橫移。
又，於晶片焊墊3之表面31上，接腳凹部34之周邊面35為隆起狀，故表面31之一部分鼓起。又，於電極引線4之表面41上，接腳凹部44之周邊面45為隆起狀，故表面41之一部分鼓起。因此，當引線框架14受到上述橫向力時，鼓起之周邊面35、45成為對於橫移之阻力。其結果可更確實防止引線框架14之橫移。
又，根據上述半導體裝置1之製造方法，如圖6B所示，利用沖壓成形工具24對與自樹脂封裝6露出之背面42為相反側之表面41之緣部43進行撞擊，藉此於電極引線4上形成接腳凹部44及防脫落部48。又，如圖6C所示，與電極引線4相同，於晶片焊墊3上形成有接腳凹部34及防脫落部38。
因此，例如由於藉由鍍敷生長而形成引線框架14，故即便引線框架14之露出面(背面32、42)由不鏽鋼基板23所覆蓋而難以自背面32、42側進行蝕刻加工之情形時，亦可確實形成防脫落部38、48(防脫落結構)。
又，由於使用可與打線接合機之毛細管交換之沖壓成形工具24，按壓引線框架14，故可將焦點集中於晶片焊墊3之周緣部33及電極引線4之緣部43，簡單且精密地形成接 腳凹部34、44。
進而，由於引線框架14係利用鍍敷法所形成，故可藉由控制鍍敷生長之時間而較薄地形成引線框架14。其結果可實現封裝之薄型化。
再者，於該第1實施形態中，例如，藉由沖壓成形工具24之撞擊而使電極引線4變形從而形成之變形部分並不限於微小之圓形之接腳凹部，亦可為例如直線狀之凹部等。
又，對接腳凹部而言，其形狀並不限於圖4及圖5所示之形狀。
例如圖7中作為第1變形例所示，亦可使用於打線接合之毛細管26(中心形成有1個微小孔27之毛細管26)對電極引線4之晶片焊墊3側之緣部43進行垂直撞擊，而形成於內部形成有1個突起28之接腳凹部29。
又，例如圖8中作為第2變形例所示，亦可使前端形成有複數個微小孔50之沖壓成形工具51對電極引線4之晶片焊墊3側之緣部43進行垂直撞擊，藉此形成內部形成有複數個突起52之接腳凹部53。
於圖7及圖8所示之引線之第1變形例及第2變形例中，由於接腳凹部29、53內形成有突起28、52，故於接腳凹部29、53中之樹脂封裝6內，突出有突起28、52。可藉由該等突起28、52，而於接腳凹部29、53內，使電極引線4(引線框架14)陷入樹脂封裝6中。因此，可使接腳凹部29、53與樹脂封裝6之嵌合結構複雜。其結果可使樹脂封裝6對接腳凹部29、53之嵌合強度提高。
又，接腳凹部無需為朝向深度方向直徑變窄之錐形，而可為例如朝向深度方向直徑變寬之倒錐形。
又，例如，亦可以不使表面41隆起於電極引線4之晶片焊墊3側之緣部43之方式，利用沖壓成形工具24以銳角對表面41進行撞擊，藉此使電極引線4向側面47側擴張而形成防脫落部48。
該情形時，可藉由將沖壓成形工具24相對於表面41之角度調節為較小，而如圖9中作為第3變形例所示，於電極引線4之表面41以不殘留沖壓成形工具24之凹痕之方式形成傾斜面49(變形部)。
另一方面，如圖10中作為第4變形例所示，可藉由將沖壓成形工具24相對於表面41之角度調節為較大，而於電極引線4之表面41形成凹部54。
再者，圖7~圖10所示之引線之第1~第4變形例之形狀亦可適用於晶片焊墊3之側面37形成有防脫落部38之情形。
又，形成於各電極引線4中之接腳凹部44之數量並不限於1個，亦可為複數個。該情形時，如圖11中作為變形例所示，複數個接腳凹部44可沿各電極引線4之緣部43之各邊彼此空開間隔進行配置。
又，背金屬層10係形成為具有Au層11、Ni層12及Cu層13各自逐層積層而成之3層結構，但並不限於此，例如，亦可將該等層之至少1種積層為複數層。該情形時，可將複數層連續積層，亦可於複數層之間插入其他種類之層。
又，背金屬層10亦可具備與Au層、Ni層及Cu層不同之 層。例如，亦可具備Ag層、Ti層等。Ti層因可對Si半導體進行歐姆接觸，而可替代Au層11進行使用。
<第2實施形態>
圖12係本發明第2實施形態之半導體裝置之模式平面圖。圖13係本發明第2實施形態之半導體裝置之模式剖面圖，且表示圖12之A'-A'截斷面之剖面。於圖12及圖13中，對於上述第1實施形態中所說明之構成使用相同參照符號表示，且省略其說明。
該第2實施形態之半導體裝置61係具有包含金屬薄板之引線框架62。構成引線框架62之金屬薄板包含主要含有Cu之Cu系素材，具體而言，包含例如純度為99.9999%(6N)以上、純度為99.99%(4N)以上之高純度銅、及Cu與異種金屬之合金(例如，Cu-Fe-P合金等)。再者，金屬薄板亦可為例如42合金(Fe-42% Ni)等之Fe系素材等。又，引線框架62(金屬薄板)之厚度例如為190μm~210μm(較佳為200μm左右)。
又，關於構成該引線框架62之晶片焊墊63及電極引線64，各自之表面65及表面66係不同於第1實施形態，而呈現未形成有凹部之平坦面。其他構成則與第1實施形態相同，而且作用效果亦相同。
再者，於第1及第2實施形態中，例如，接合層15之副層無需為Cu-Sn合金層17、18，亦可為例如含有Cu與不含Cu及Pb之異種金屬即Zn之合金、且含有Cu作為主成分之Cu-Zn合金層。
又，例如，引線框架62之表面(晶片焊墊63之表面65及電極引線64之表面66)無需為非被覆面。舉其一例而言，如圖14中作為第2實施形態之變形例所示，亦可藉由實施鍍敷或濺鍍處理而形成被覆層67。
被覆層67係於晶片焊墊63之表面65上，如圖15所示形成為自晶片焊墊63側依序積層有Ag層68及引線框架側Cu層69之2層結構。可藉由於Ag層68上積層引線框架側Cu層69，而使Cu露出於晶片焊墊63之與半導體晶片2對向之整個面(表面65)。
另一方面，於電極引線64之表面66上，被覆層67如圖16所示形成為僅形成有Ag層68之單層結構。藉此，可使Ag露出於接線5之整個連接面。因此，作為連接於電極引線4之接線5，不僅可利用Cu線，亦可利用Au線等各種金屬線。
於該變形例之情形時，例如亦可將引線框架側Cu層69用作本發明之晶片焊墊之一例。藉此，可省略引線框架62(無引線框架)。以上，已說明本發明之實施形態，但本發明亦可以其他形態實施。
例如，上述實施形態係以QFN型半導體裝置為例進行說明，但本發明亦可應用於QFP(Quad Flat Package)、SOP(Small Outline Package)等其他種類之封裝型之半導體裝置。
又，本發明之實施形態僅為用於明確本發明之技術內容之具體例，不應將本發明以該等具體例進行限定解釋，本 發明之精神及範圍僅由隨附之申請專利範圍所限定。
又，本發明之各實施形態中呈現之構成要素可於本發明之範圍內加以組合。
本申請案係與2009年10月20日日本專利廳提出之特願2009-241550號及2009年10月20日日本專利廳提出之特願2009-241551號對應，該等申請中之所有揭示以引用之方式併入於此。
1、61‧‧‧半導體裝置
2‧‧‧半導體晶片
3、63‧‧‧晶片焊墊
4、64‧‧‧電極引線
5‧‧‧接線
6‧‧‧樹脂封裝
7‧‧‧Si基板
8‧‧‧焊墊開口
9‧‧‧電極焊墊
10‧‧‧背金屬層
11‧‧‧Au層
12‧‧‧Ni層
13‧‧‧Cu層
14、62‧‧‧引線框架
15‧‧‧接合層
16‧‧‧Bi系材料層
17‧‧‧Cu-Sn合金層
18‧‧‧Cu-Sn合金層
19‧‧‧晶片焊墊背面鍍敷層
20‧‧‧引線背面鍍敷層
21‧‧‧(半導體晶片之)表面
22‧‧‧(半導體晶片之)背面
23‧‧‧不鏽鋼基板
24、51‧‧‧沖壓成形工具
25‧‧‧接合膏
26‧‧‧毛細管
27、50‧‧‧孔
28、52‧‧‧突起
29、34、44、53‧‧‧接腳凹部
31、65‧‧‧(晶片焊墊之)表面
32‧‧‧(晶片焊墊之)背面
33‧‧‧(晶片焊墊之)周緣部
35‧‧‧(晶片焊墊之)周邊面
36‧‧‧裝載面
37‧‧‧(晶片焊墊之)側面
38‧‧‧(晶片焊墊之)防脫落部
41、66‧‧‧(電極引線之)表面
42‧‧‧(電極引線之)背面
43‧‧‧(電極引線之)緣部
45‧‧‧(電極引線之)周邊面
46‧‧‧連接面
47‧‧‧(電極引線之)側面
48‧‧‧(電極引線之)防脫落部
49‧‧‧傾斜面
54‧‧‧凹部
67‧‧‧被覆層
68‧‧‧Ag層
69‧‧‧引線框架側Cu層
圖1係本發明第1實施形態之半導體裝置之模式平面圖。
圖2係本發明第1實施形態之半導體裝置之模式剖面圖，且表示圖1之A-A截斷面之剖面。
圖3係圖2之由虛線圓B所包圍之部分之主要部分放大圖。
圖4係圖2之由虛線圓C所包圍之部分之主要部分放大圖。
圖5係圖2之由虛線圓D所包圍之部分之主要部分放大圖。
圖6A係表示圖1及圖2所示之半導體裝置之製造步驟之一部分之模式剖面圖。
圖6B係表示圖6A之下一步驟之模式剖面圖。
圖6C係表示圖6B之下一步驟之模式剖面圖。
圖6D係表示圖6C之下一步驟之模式剖面圖。
圖6E係表示圖6D之下一步驟之模式剖面圖。
圖6F係表示圖6E之下一步驟之模式剖面圖。
圖6G係表示圖6F之下一步驟之模式剖面圖。
圖7係表示圖3所示之引線之第1變形例之圖。
圖8係表示圖3所示之引線之第2變形例之圖。
圖9係表示圖3所示之引線之第3變形例之圖。
圖10係表示圖3所示之引線之第4變形例之圖。
圖11係表示圖1所示之接腳凹部之配置形態之變形例之圖。
圖12係本發明第2實施形態之半導體裝置之模式平面圖。
圖13係本發明第2實施形態之半導體裝置之模式剖面圖，且表示圖12之A'-A'截斷面之剖面。
圖14係表示圖13所示之引線框架之變形例之圖。
圖15係圖14之由虛線圓F所包圍之部分之主要部分放大圖。
圖16係圖14之由虛線圓G所包圍之部分之主要部分放大圖。
1‧‧‧半導體裝置
2‧‧‧半導體晶片
3‧‧‧晶片焊墊
4‧‧‧電極引線
7‧‧‧Si基板
8‧‧‧焊墊開口
9‧‧‧電極焊墊
14‧‧‧引線框架
21‧‧‧(半導體晶片之)表面
31‧‧‧(晶片焊墊之)表面
33‧‧‧(晶片焊墊之)周緣部
34、44‧‧‧接腳凹部
35‧‧‧(晶片焊墊之)周邊面
37‧‧‧(晶片焊墊之)側面
38‧‧‧(晶片焊墊之)防脫落部
41‧‧‧(電極引線之)表面
43‧‧‧(電極引線之)緣部
45‧‧‧(電極引線之)周邊面
46‧‧‧連接面
47‧‧‧(電極引線之)側面
48‧‧‧(電極引線之)防脫落部

Claims (24)

  1. 一種半導體裝置，其係具有樹脂封裝之樹脂密封型半導體裝置，且包含：引線框架，其包含表面含有Cu之晶片焊墊(die pad)及配置於上述晶片焊墊之周圍之複數條引線；半導體晶片，其包含形成背面之Cu層，且以與上述晶片焊墊之上述表面對向之方式配置；及接合層，其位於上述晶片焊墊與上述半導體晶片之間；且上述接合層係包含Bi系材料層、及相對於該Bi系材料層自上述晶片焊墊與上述半導體晶片之對向方向之兩側夾住上述Bi系材料層之不含Pb之Cu合金層；使上述引線框架之背面成為自上述樹脂封裝中露出之露出面，且上述引線框架之表面成為藉由上述樹脂封裝而被密封之密封面；上述引線框架之上述引線包含：變形部，其係上述密封面變形而形成者；及突出部，其係形成於上述變形部之側方，且於上述樹脂封裝內自其側面突出；於觀視剖面時，上述突出部之前端與上述引線之上述露出面的連接線為非直線狀。
  2. 一種半導體裝置，其係具有樹脂封裝之樹脂密封型半導體裝置，且包含：引線框架，其包含具有表面及背面且該表面含有Cu之 晶片焊墊及配置於上述晶片焊墊之周圍之複數條引線；半導體晶片，其具有表面及背面，且包含形成該背面之Cu層，並以與上述晶片焊墊之上述表面對向之方式配置；及接合層，其位於上述晶片焊墊與上述半導體晶片之間；上述接合層係包含Bi系材料層、及相對於該Bi系材料層自上述晶片焊墊與上述半導體晶片之對向方向之兩側夾住上述Bi系材料層之不含Pb之Cu合金層；使上述引線框架之背面成為自上述樹脂封裝中露出之露出面，且上述引線框架之表面成為藉由上述樹脂封裝而被密封之密封面；上述引線框架之上述引線包含：變形部，其係上述密封面變形而形成者；及突出部，其係形成於上述變形部之側方，且於上述樹脂封裝內自其側面突出；於觀視剖面時，上述突出部之前端與上述引線之上述露出面的連接線為非直線狀。
  3. 如請求項1或2之半導體裝置，其中上述Cu合金層之至少一層係為Cu-Sn合金層。
  4. 如請求項1或2之半導體裝置，其中上述Cu合金層之至少一層係為Cu-Zn合金層。
  5. 如請求項1之半導體裝置，其中上述半導體晶片係包含：在背面側形成有上述Cu層之 Si基板；且於上述Si基板與上述Cu層之間，形成有可對Si半導體進行歐姆接觸之金屬層。
  6. 如請求項1或2之半導體裝置，其中上述變形部係為藉由上述密封面朝向上述引線框架之厚度方向凹陷而形成之凹部。
  7. 如請求項6之半導體裝置，其中上述密封面之上述凹部之周邊部係呈現隆起狀。
  8. 如請求項6之半導體裝置，其中於上述凹部內形成有突起。
  9. 如請求項6之半導體裝置，其中上述引線框架係含有Cu。
  10. 如請求項9之半導體裝置，其中上述晶片焊墊係具有形成其表面之引線框架側Cu層、及形成於該引線框架側Cu層之正下方之不含Cu之金屬層的積層構造。
  11. 如請求項1之半導體裝置，其中於上述半導體晶片之表面形成有電極焊墊。
  12. 如請求項11之半導體裝置，其中上述電極焊墊係含有包含Al之金屬材料。
  13. 如請求項5之半導體裝置，其中形成於上述Si基板與上述Cu層之間之上述金屬層係Au層。
  14. 如請求項13之半導體裝置，其中 上述半導體裝置進而包含形成於上述Si基板與上述Au層之間之Ni層。
  15. 如請求項1或2之半導體裝置，其中上述半導體晶片係包含：在背面側形成有上述Cu層之Si基板；於上述Si基板與上述Cu層之間，形成有可對Si半導體進行歐姆接觸之金屬層；且上述Si基板之厚度係220μm~240μm。
  16. 如請求項1或2之半導體裝置，其中上述引線框架係藉由鍍敷法而形成。
  17. 如請求項16之半導體裝置，其中上述引線框架之厚度係為10μm~50μm。
  18. 如請求項11之半導體裝置，其中上述晶片焊墊係俯視為四角形者；上述複數條引線係以包圍該晶片焊墊之四周之方式而配置。
  19. 如請求項18之半導體裝置，其中上述晶片焊墊係俯視時大於上述半導體晶片之四角形；上述晶片焊墊之上述密封面之上述周緣部係包圍上述半導體晶片。
  20. 如請求項1之半導體裝置，其中上述Bi系材料層之厚度與上述Cu合金層之厚度之和即上述接合層之總厚度係12μm~36μm。
  21. 如請求項1之半導體裝置，其中上述Bi系材料層之厚度係10μm~30μm。
  22. 如請求項1之半導體裝置，其中上述Cu合金層之厚度係1μm~3μm。
  23. 一種半導體裝置之製造方法，其包含下述步驟：準備引線框架，其包含表面含有Cu之晶片焊墊及配置於上述晶片焊墊之周圍之複數條引線；藉由使上述引線框架之上述引線之表面變形，而形成變形部及自上述引線框架之側面突出之突出部；準備在背面包含Cu層之半導體晶片；以經由接合材使上述Cu層與上述接合材接觸之方式，將上述半導體晶片接合於上述晶片焊墊上，該接合材含有：不含Cu及Pb之異種金屬、及Bi系材料；於上述半導體晶片接合後，對上述引線框架進行熱處理；於上述引線框架之熱處理後，以使上述引線框架之背面露出之方式，將上述引線框架之表面藉由上述樹脂封裝予以密封；及形成上述突出部之步驟係以使上述突出部之前端與上述引線之上述露出面的連接線為非直線狀之方式，形成上述突出部。
  24. 如請求項23之半導體裝置之製造方法，其中上述半導體晶片係包含Si基板；上述準備半導體晶片之步驟係包含下述步驟： 於上述Si基板之背面，形成可對Si半導體進行歐姆接觸之金屬層；及於該金屬層上形成上述Cu層。
TW099135788A 2009-10-20 2010-10-20 Semiconductor device and method for manufacturing semiconductor device TWI480993B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009241551 2009-10-20
JP2009241550 2009-10-20

Publications (2)

Publication Number Publication Date
TW201135890A TW201135890A (en) 2011-10-16
TWI480993B true TWI480993B (zh) 2015-04-11

Family

ID=43900351

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099135788A TWI480993B (zh) 2009-10-20 2010-10-20 Semiconductor device and method for manufacturing semiconductor device

Country Status (4)

Country Link
US (2) US9666501B2 (zh)
JP (1) JPWO2011049128A1 (zh)
TW (1) TWI480993B (zh)
WO (1) WO2011049128A1 (zh)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5630060B2 (ja) * 2010-04-02 2014-11-26 富士通株式会社 はんだ接合方法、半導体装置及びその製造方法
CN102683221B (zh) * 2011-03-17 2017-03-01 飞思卡尔半导体公司 半导体装置及其组装方法
JP5723225B2 (ja) * 2011-06-03 2015-05-27 パナソニック株式会社 接合構造体
US10043960B2 (en) * 2011-11-15 2018-08-07 Cree, Inc. Light emitting diode (LED) packages and related methods
WO2013099243A1 (ja) * 2011-12-27 2013-07-04 パナソニック株式会社 接合構造体
CN103681557B (zh) * 2012-09-11 2017-12-22 恩智浦美国有限公司 半导体器件及其组装方法
DE102015102453A1 (de) * 2015-02-20 2016-08-25 Heraeus Deutschland GmbH & Co. KG Bandförmiges Substrat zur Herstellung von Chipkartenmodulen, Chipkartenmodul, elektronische Einrichtung mit einem derartigen Chipkartenmodul und Verfahren zur Herstellung eines Substrates
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
JP6149072B2 (ja) * 2015-07-07 2017-06-14 アオイ電子株式会社 半導体装置およびその製造方法
US9741617B2 (en) * 2015-11-16 2017-08-22 Amkor Technology, Inc. Encapsulated semiconductor package and method of manufacturing thereof
DE102016109349A1 (de) * 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts
JP6857035B2 (ja) * 2017-01-12 2021-04-14 ローム株式会社 半導体装置
US9972558B1 (en) * 2017-04-04 2018-05-15 Stmicroelectronics, Inc. Leadframe package with side solder ball contact and method of manufacturing
US10008454B1 (en) * 2017-04-20 2018-06-26 Nxp B.V. Wafer level package with EMI shielding
US10079198B1 (en) 2017-05-31 2018-09-18 Stmicroelectronics, Inc. QFN pre-molded leadframe having a solder wettable sidewall on each lead
US11367619B2 (en) * 2017-08-17 2022-06-21 Semiconductor Components Industries, Llc Semiconductor package electrical contacts and related methods
IT201700103511A1 (it) * 2017-09-15 2019-03-15 St Microelectronics Srl Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione
JP2019083295A (ja) * 2017-10-31 2019-05-30 トヨタ自動車株式会社 半導体装置
TW201926608A (zh) * 2017-12-07 2019-07-01 晨星半導體股份有限公司 晶片封裝結構
US20190206770A1 (en) * 2017-12-29 2019-07-04 Texas Instruments Incorporated Integrated circuit package with lead lock
CN110265376A (zh) * 2018-03-12 2019-09-20 意法半导体股份有限公司 引线框架表面精整
US10763195B2 (en) * 2018-03-23 2020-09-01 Stmicroelectronics S.R.L. Leadframe package using selectively pre-plated leadframe
CN110945649B (zh) * 2018-05-29 2023-06-16 新电元工业株式会社 半导体模块
US10777489B2 (en) * 2018-05-29 2020-09-15 Katoh Electric Co., Ltd. Semiconductor module
US20200043833A1 (en) * 2018-07-31 2020-02-06 Texas Instruments Incorporated Lead frame for a die
SG10201811582WA (en) * 2018-12-24 2020-07-29 Delta Electronics Int’L Singapore Pte Ltd Package structure and manufacturing method thereof
US11735512B2 (en) 2018-12-31 2023-08-22 Stmicroelectronics International N.V. Leadframe with a metal oxide coating and method of forming the same
JP7338204B2 (ja) * 2019-04-01 2023-09-05 富士電機株式会社 半導体装置
US11837532B2 (en) * 2020-01-15 2023-12-05 Texas Instruments Incorporated Leadframe with delamination resistant feature
CN112317972B (zh) * 2020-09-30 2021-07-20 厦门大学 一种单向性耐高温焊接接头的低温快速制造方法
JP7451455B2 (ja) * 2021-03-19 2024-03-18 株式会社東芝 半導体装置
JP2022146270A (ja) * 2021-03-22 2022-10-05 ローム株式会社 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001179483A (ja) * 1999-12-24 2001-07-03 Toyota Central Res & Dev Lab Inc 電子部品の実装構造体およびその製造方法
TW544881B (en) * 2000-12-28 2003-08-01 Hitachi Ltd Semiconductor device
JP2007281412A (ja) * 2006-03-17 2007-10-25 Toyota Central Res & Dev Lab Inc パワー半導体モジュール
JP2008211101A (ja) * 2007-02-27 2008-09-11 Dowa Electronics Materials Co Ltd 半田層及びそれを用いたデバイス接合用基板並びにその製造方法
TW200924093A (en) * 2007-10-30 2009-06-01 Monolithic Power Systems Inc Flip-chip interconnect structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3062192B1 (ja) * 1999-09-01 2000-07-10 松下電子工業株式会社 リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
JP2006253732A (ja) 2000-12-28 2006-09-21 Renesas Technology Corp 半導体装置
US7358106B2 (en) * 2005-03-03 2008-04-15 Stellar Micro Devices Hermetic MEMS package and method of manufacture
JP4569423B2 (ja) 2005-08-31 2010-10-27 株式会社日立製作所 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001179483A (ja) * 1999-12-24 2001-07-03 Toyota Central Res & Dev Lab Inc 電子部品の実装構造体およびその製造方法
TW544881B (en) * 2000-12-28 2003-08-01 Hitachi Ltd Semiconductor device
JP2007281412A (ja) * 2006-03-17 2007-10-25 Toyota Central Res & Dev Lab Inc パワー半導体モジュール
JP2008211101A (ja) * 2007-02-27 2008-09-11 Dowa Electronics Materials Co Ltd 半田層及びそれを用いたデバイス接合用基板並びにその製造方法
TW200924093A (en) * 2007-10-30 2009-06-01 Monolithic Power Systems Inc Flip-chip interconnect structure

Also Published As

Publication number Publication date
JPWO2011049128A1 (ja) 2013-03-14
US9666501B2 (en) 2017-05-30
US9847280B2 (en) 2017-12-19
US20120205790A1 (en) 2012-08-16
TW201135890A (en) 2011-10-16
WO2011049128A1 (ja) 2011-04-28
US20170243811A1 (en) 2017-08-24

Similar Documents

Publication Publication Date Title
TWI480993B (zh) Semiconductor device and method for manufacturing semiconductor device
US7879653B2 (en) Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same
US7271497B2 (en) Dual metal stud bumping for flip chip applications
US7148080B2 (en) Method for joining lead frames in a package assembly, method for forming a chip stack package, and a chip stack package
TWI427716B (zh) 無載具之半導體封裝件及其製法
US8975734B2 (en) Semiconductor package without chip carrier and fabrication method thereof
JP2005520339A (ja) ウエハレベルのコーティングされた銅スタッドバンプ
TW200818458A (en) Stackable packages for three-dimensional packaging of semiconductor dice
JP7089388B2 (ja) 半導体装置および半導体装置の製造方法
US8786084B2 (en) Semiconductor package and method of forming
US7952198B2 (en) BGA package with leads on chip
US7825501B2 (en) High bond line thickness for semiconductor devices
JP2003174131A (ja) 樹脂封止型半導体装置及びその製造方法
US7109587B1 (en) Apparatus and method for enhanced thermal conductivity packages for high powered semiconductor devices
JP2022103594A (ja) リードフレーム、リードフレームの製造方法及び半導体装置
US9589815B2 (en) Semiconductor IC packaging methods and structures
CN113410201A (zh) 半导体装置、引线架以及半导体装置的制造方法
JPH0590465A (ja) 半導体装置
TW202036806A (zh) 半導體元件搭載用基板
US11227820B2 (en) Through hole side wettable flank
CN115148697A (zh) 半导体封装结构及其制造方法
TW202236537A (zh) 半導體封裝結構及導線架
EP3024025A1 (en) Die arrangement
KR20020094965A (ko) 리드프레임 및 이를 이용한 반도체패키지
JPH0686339U (ja) 混成集積回路基板