CN1197149C - 具有下弯部扰流板结构的封装构件 - Google Patents

具有下弯部扰流板结构的封装构件 Download PDF

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CN1197149C
CN1197149C CN 00133370 CN00133370A CN1197149C CN 1197149 C CN1197149 C CN 1197149C CN 00133370 CN00133370 CN 00133370 CN 00133370 A CN00133370 A CN 00133370A CN 1197149 C CN1197149 C CN 1197149C
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张月琼
赖雅怡
侯至聪
黄焜铭
叶清昆
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Siliconware Precision Industries Co Ltd
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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Abstract

一种具有下弯部扰流板结构的封装构件，至少包括：一导线架、一芯片、一粘着层、多个扰流板、上胶体、以及下胶体。其中导线架具多个导脚，藉由粘着层将芯片配置于导脚下。位于芯片的两侧具有二片扰流板，而扰流板的第一弯曲与第二弯曲形成下弯而产生一空间。藉由调整第一弯曲与第二弯曲形成所空间的大小，以达到上下模组件内的胶体比例平衡，使其在冷凝时收缩量相等，防止封装构件扭曲变形。

Description

具有下弯部扰流板结构的封装构件
技术领域
本发明涉及一种具有下弯部扰流板结构的封装构件。
背景技术
在现今信息爆炸的世界，集成电路已与日常生活有密不可分的关系，无论在食衣住行还是娱乐方面，都常会用到集成电路元件所组成的产品。随着电子科技的不断演进，更人性化、功能性更复杂的电子产品不断推陈出新，然而各种产品无不朝向轻、薄、短、小的趋势设计，以提供更便利舒适的使用。
在半导体制造工艺上，已迈入0.18微米集成电路的大量生产时代，集成度更高的半导体产品已垂手可得。而集成电路(Integrated Circuits，IC)的生产，主要分为三个阶段：硅芯片的制造、集成电路的制作以及集成电路的封装(Package)等。就集成电路的封装而言，此即是完成集成电路成品的最后步骤。封装的目的在于提供芯片(Die)与印刷电路板(Printed Circuit Board，PCB)或其他适当元件之间电连接的媒介及保护芯片。
在完成半导体制造工艺后，芯片由晶片(Wafer)切割形成。一般在芯片的周边具有焊垫(Bonding Pad)，其作用为提供芯片检测的测试点，以及提供芯片与其他元件间连接的端点。为了连接芯片和其他元件，因此必须使用导线(Wire)或凸块(Bump)作为连接的媒介。
对一般的半导体存储器而言，如动态随机存取存储器(Dynamic RandomAccess Memory，DRAM)，其芯片所使用的封装的方式，目前主要有J型小外型引脚封装(Small Outline J-Lead，SOJ)，与薄小外型引脚封装(Thin SmallOutline Package，TSOP)两种。
然而，值得一提的是，在小外型J型引脚封装(SOJ)或薄小外型引脚封装(TSOP)中，就导线架(Lead Frame)而言，又可区分为芯片上有导脚封装(Lead On Chip，LOC)，主要做为动态随机存取存储器(DRAM)的封装结构，其优点为传输速度快、散热佳、以及结构小，为IBM在1988年的发明，比如US 4,862,245。或导脚上有芯片封装(Chip On Lead COL)，如US 4,989,068等的导线架。
请参照图1，其所绘示为现有小外型引脚封装LOC架构剖面示意图。
如图1所示，以现有芯片上有导脚封装(LOC)为例，其中芯片108利用粘着层110固定于导脚109下，再覆盖以封装胶体(Mold Compound)，具有上胶体106及下胶体102，以封装成型。上胶体106具有厚度116，而下胶体102具有厚度114，而厚度116与厚度114的比例为1∶3，封装后会因上下胶体的厚度及体积不同，因此上胶体106与下胶体102在冷凝时收缩量亦不同，而导致整个封装构件产生扭曲变形(Warpage)。
发明内容
因此，本发明就是在提供一种具有下弯部扰流板结构的封装构件，以达到上下胶体的体积比例平衡，使其在冷凝时收缩量相等，而防止封装构件扭曲变形。
为此，本发明提供一种具有下弯部扰流板结构的封装构件，至少包括：一导线架，具有多个导脚；一芯片，粘置于该导线架的该些导脚下；多个扰流板，位于该芯片的两侧，至少具有一第一弯曲与一第二弯曲；以及一封装胶体，包括一上胶体、以及一下胶体，覆盖于该导线架的上、下方；其中该第一弯曲与该第二弯曲体形成一空间，藉由调整该些空间的大小，使该上胶体与该下胶体具有相同的体积。
附图说明
为使本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举一优选实施例，并配合附图作详细说明。附图中：
图1所绘示为现有小型外引脚封装LOC架构剖面示意图；
图2绘示依照本发明优选实施例一种具有下弯部的扰流板结构剖面示意图；以及
图3A及图3B绘示依照本发明优选实施例一种具有下弯部的扰流板结构平面及半剖面示意图。
附图的标示说明：
102、202：下胶体
106、206：上胶体
104、204：导线架
108、208：芯片
110、210：粘着层
114、116：厚度
216：第一弯曲
218：第二弯曲
220：扰流板
222：空间
109、224：导脚
302：开孔
具体实施方式
实施例
请参照图2，其所绘示为依照本发明的优选实施例一种具有下弯部的扰流板结构剖面示意图。在此实施例中，是以承载器为导线架且芯片上有导脚封装(Lead On Chip，LOC)的型式为例来作说明。
如图2所示，本发明的具有下弯部的扰流板结构，应用于半导体的导线架型态封装构件，至少包括：一导线架204、一芯片208、一粘着层210、数个扰流板220、上胶体206、以及下胶体202，其中导线架204具有多个导脚224。
本发明的具有下弯部的扰流板结构采用导线架204作为承载器，而导线架204包括：多个导脚(lead)224，藉由粘着层210将芯片208配置于导脚224下。其中粘着层可为聚亚酰胺(Polyimide)或不导电胶。导脚224又可细分为内导脚部分及外导脚部分。而芯片208比如是动态随机存取存储器(DRAM)、只读存储器(ROM)、静态随机存取存储器(SRAM)、快闪存储器(Flash Memory)、逻辑电路芯片(LOGIC)或模拟芯片(ANALOG)等各种集成电路芯片，均可应用于本发明的封装中。芯片208的表面上均具有多个金属垫(pad)，至于芯片208与导线架204电接合部分，可以利用现有导线接合方式(wire bonding)，以线型导电材料，比如金线、铝线或其他金属线，将金属垫与导脚224的内导脚部分导电地连接。
位于芯片208的两侧具有二片扰流板220，而扰流板220的第一弯曲216与第二弯曲218形成下弯而产生一空间222。最后，覆盖封装胶体206于导线架204的上、下方。藉由调整第一弯曲216与第二弯曲218所形成空间222的大小，可使上胶体206与该下胶体202具有相同的体积，并完成最后包装及成型的部分。
其中，上胶体206与下胶体202的材质，比如是环氧树脂(Epoxy)等绝缘材质，具有相同的体积，可使其在冷凝时收缩量相等，而防止封装构件的扭曲变形。
请参照图3A及图3B，其所绘示依照本发明优选实施例一种具有下弯部的扰流板结构平面及半剖面示意图。
如图3A所示，在具有下弯部的扰流板结构的上视图中，可观察到扰流板220还包括数个开孔302，目的是为了在不影响模流的情况下，改善应力分布的问题，增强封装构件的结构力。
如图3B所示，其所绘示依照本发明优选实施例一种具有下弯部的扰流板结构半剖面示意图。为对应图3A的3B-3B剖视图，亦为2A的部分详图，仅以半剖面的方式绘示。而后续将外导脚折弯成型(forming)的部分，以及外导脚与电路板间以表面封装技术(Surface Mount Technique，SMT)接合部分，由于与现有技术相同，在此不再赘述。
根据本发明，提出一种具有下弯部扰流板结构的封装构件，至少包括：一导线架，具有多个导脚；一芯片，粘置于该导线架的该些导脚下；一粘着层，介于该芯片与该导线架的该些导脚间，用以固定该些芯片；多个扰流板，位于该芯片的两侧，至少具有一第一弯曲与一第二弯曲；以及一封装胶体，包括一上胶体、以及一下胶体，覆盖于该导线架的上、下方；其中该第一弯曲与该第二弯曲体形成一空间，藉由调整该些空间的大小，使上胶体与该下胶体具有大致上相同的体积。
依照本发明的优选实施例，本发明具有下弯部扰流板结构的封装构件，可藉由调整第一弯曲与第二弯曲形成所空间的大小，使上胶体与该下胶体具有相同的体积。其在冷凝时收缩量相等，因而防止封装构件的扭曲变形。
综上所述，本发明至少具有下列优点：
1.在原有的导线架的两侧设置二片扰流板，其中扰流板在第一弯曲与第二弯曲形成下弯而产生一空间，即可使填入的上胶体与下胶体的体积比例平衡，使其在凝时收缩量相等，防止封装构件的扭曲变形。
2.在扰流板开设数个开孔，可在不影响模流的情况下，改善应力分布的问题，增强封装构件的结构力。
虽然本发明已结合一优选实施例揭露如上，然而其并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作出更动与润饰，因此本发明的保护范围应当由后附的权利要求所界定。

Claims (8)

1.一种具有下弯部扰流板结构的封装构件，至少包括：
一导线架，具有多个导脚；
一芯片，粘置于该导线架的该些导脚下；
多个扰流板，位于该芯片的两侧，至少具有一第一弯曲与一第二弯曲；以及
一封装胶体，包括一上胶体、以及一下胶体，覆盖于该导线架的上、下方；
其中该第一弯曲与该第二弯曲体形成一空间，藉由调整该些空间的大小，使该上胶体与该下胶体具有相同的体积。
2.如权利要求1所述的具有下弯部扰流板结构的封装构件，其中该封装胶体的材质为环氧树脂。
3.如权利要求1所述的具有下弯部扰流板结构的封装构件，其中该扰流板还包括多个开孔。
4.如权利要求1所述的具有下弯部扰流板结构的封装构件，还包括：
一粘着层，介于该芯片与该导线架的该些导脚间，用以固定该芯片。
5.如权利要求4所述的具有下弯部扰流板结构的封装构件，其中该封装胶体的材质为环氧树脂。
6.如权利要求4所述的具有下弯部扰流板结构的封装构件，其中该粘着层的材质为聚亚酰胺。
7.如权利要求4所述的具有下弯部扰流板结构的封装构件，其中该粘着层的材质为不导电胶。
8.如权利要求4所述的具有下弯部扰流板结构的封装构件，其中该扰流板还包括多个开孔。
CN 00133370 2000-11-27 2000-11-27 具有下弯部扰流板结构的封装构件 Expired - Fee Related CN1197149C (zh)

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TWI283488B (en) 2005-07-27 2007-07-01 Chipmos Technologies Inc Chip package
CN100421237C (zh) * 2005-08-08 2008-09-24 南茂科技股份有限公司 不对称铸模的芯片封装体
CN101540307B (zh) * 2008-03-20 2010-10-20 力成科技股份有限公司 引脚在芯片上的半导体封装构造
CN101794761A (zh) * 2010-03-23 2010-08-04 张轩 一种ic封装用的引线框架
CN107026091A (zh) * 2017-05-16 2017-08-08 杰群电子科技（东莞）有限公司 一种半导体生产工艺及装置

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