CN2919531Y - 一种改进的半导体芯片封装的引线框架结构 - Google Patents

一种改进的半导体芯片封装的引线框架结构 Download PDF

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CN2919531Y
CN2919531Y CNU200620042538XU CN200620042538U CN2919531Y CN 2919531 Y CN2919531 Y CN 2919531Y CN U200620042538X U CNU200620042538X U CN U200620042538XU CN 200620042538 U CN200620042538 U CN 200620042538U CN 2919531 Y CN2919531 Y CN 2919531Y
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施震宇
曾小光
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KUIHE PRECISION ELECTRONIC (SHANGHAI) CO Ltd
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KUIHE PRECISION ELECTRONIC (SHANGHAI) CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

本实用新型公开了一种改进的半导体芯片封装的引线框架结构，至少包括作为芯片载体的引线框架、金线，其中所述的引线框架包括载片台和引线框架配线单元，所述引线框架配线单元具有弯沉部，所述弯沉部贴近所述载片台设置，所述弯沉部与所述引线配线单元以倾斜面或垂直面连接，来减小载片台的贴片区域和引线配线单元之间的落差。这种改进的结构不仅实现简单方便，而且能够达到满意的效果，有效减小了金线的落差，增强了金线的抗冲击性，并有效降低了封装成本。

Description

一种改进的半导体芯片封装的引线框架结构
技术领域
本实用新型涉及一种半导体封装的引线框架结构，尤其涉及一种改进的半导体芯片封装的引线框架结构，属于半导体分立器件技术领域。
背景技术
在现有的半导体封装的数十种常用封装技术中，比较常用的是采用金属(铜、镍)引线框架的方案，如DIP、SOP、TSOP、QFP、PLC、DPAK和TO系列等，图1(a)是现有技术的半导体芯片引线框架装配结构示意图，此类方案，以金属引线框架为芯片载体，具体地，芯片放置在载片台1上，芯片2通过金线3与引线框架配线区域4相连并向外引出，用塑封材料将其密封。
在现有技术普遍的设计中，特别是TO系列如TO22O/TO251/TO252产品的引线框架设计中，引线框架配线区域4与载片台1区域有一较大落差，如图1(b)所示。对于上述封装形式，由于半导体芯片厚度普遍较小，造成配线落差较大。这导致两个问题：一是配线落差大，导致配线弧度较大，在随后的塑封工序中容易被塑封冲弯，容易导致短路；二是落差过大，致使所用的金线较长，使得材料浪费，在大批量生产的情况下会造成封装成本的提高。
实用新型内容
本实用新型的目的是针对现有技术的不足，提出一种改进的引线框架配线区域的结构，通过将引线配线区域向载片台方向弯折下沉，降低配线的落差，这种改进的结构在维持了产品成品原有的外形尺寸的基础上，不仅实现简单方便，而且能够达到满意的效果，有效减小了金线的落差，增强了金线的抗冲击性，并有效降低了成本。
为实现上述目的，本实用新型提供了一种半导体芯片封装结构，至少包括作为芯片载体的引线框架、金线，其中所述的引线框架包括载片台和引线框架配线单元，所述引线配线单元向或/和所述载片台通过弯折来减小两者之间的落差。
较佳地，所述引线配线单元具有弯沉部，所述弯沉部贴近所述载片台设置，所述弯沉部与所述引线配线单元以倾斜面连接。
较佳地，所述引线配线单元具有弯沉部，所述弯沉部贴近所述载片台设置，所述弯沉部与所述引线配线单元以垂直面连接。
本实用新型与现有技术相比，其优点在于：通过将引线配线单元打弯下沉，有效地减小了两者的落差，进而减小了连接两者的金线的落差，增强了金线的抗冲击性，同时也节约了金线用量、减少了产品成本。
附图说明
图1(a)是现有技术的半导体芯片引线框架示意图；
图1(b)是图1(a)所示现有引线框架侧视图；
图2(a1)是本实用新型的一个实施例的示意图，其中引线框架配线单元以打弯方式向载片台弯沉；
图2(a2)是图2(a1)的侧视图；
图2(b1)是本实用新型的另一个实施例的示意图，其中引线框架配线单元以剪切方式向载片台弯沉；
图2(b2)是图2(b1)的侧视图。
具体实施方式
以下将结合附图对本实用新型的构思、具体结构及产生的技术效果作进一步说明，以充分地了解本实用新型。
图2(a1)、图2(a2)是本实用新型一种改进的半导体芯片封装的引线框架结构的一个实施例，其中，改进的半导体芯片引线框架配线单元弯沉的示意图；如图2(a2)所示，将引线框架的配线单元4向载片台1(Pad)方向打弯下沉形成一弯沉部，使金线3的落差大幅度降低，从而使得金线3配线的弧度降低。这样不仅有效地节约了金线；同时由于其线长缩短，使得金线的抗冲击能力也得到了加强，使其在塑封灌胶时不易弯曲，避免了短路的现象。特别的，还可以通过减小金线线径来降低封装成本。
图2(b1)、图2(b2)所示是本实用新型改进的引线框架配线单元弯沉的又一实施例，其引线框架配线单元4以剪切方式向载片台1方向弯沉形成一弯沉部。其同样达到前述优点。所述剪切方式是，配线单元需要弯沉的两个部位是分别沿垂直方向反方向错位拉伸，以形成剪切式的错位弯沉；较佳地是错位拉伸半个配线单元的材料厚度。
另外需要说明的是，本实用新型所述的引线框架结构同样适用于DIP、TSOP、QFP、PLC等以金属引线框架为芯片载体，芯片通过金线与引线框架配线区域相连并向外引出，用塑封材料将其密封的封装形式。
最后所应说明的是，以上实施例仅用以说明本实用新型的技术方案而非限制，尽管参照较佳实施例对本实用新型进行了详细说明，本领域的普通技术人员应当理解，可以对本实用新型的技术方案进行修改或等同替换，而不脱离本实用新型技术方案的精神和范围，其均应涵盖在本实用新型的权利要求范围之中。

Claims (3)

1.一种改进的半导体芯片封装的引线框架结构，至少包括作为芯片载体的引线框架，其中所述的引线框架包括载片台和引线框架配线单元，其特征在于，所述引线配线单元向所述载片台弯沉，从而减小两者之间的落差。
2.根据权利要求1所述的半导体芯片封装的引线框架结构，其特征在于，所述引线配线单元具有弯沉部，所述弯沉部贴近所述载片台设置，所述弯沉部与所述引线配线单元以倾斜面连接。
3.根据权利要求1所述的半导体芯片封装的引线框架结构，其特征在于，所述引线配线单元具有弯沉部，所述弯沉部贴近所述载片台设置，所述弯沉部与所述引线配线单元以垂直面连接。
CNU200620042538XU 2006-06-08 2006-06-08 一种改进的半导体芯片封装的引线框架结构 Expired - Lifetime CN2919531Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103560123A (zh) * 2013-10-28 2014-02-05 沈健 一种打弯部分倾斜的引线框架

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103560123A (zh) * 2013-10-28 2014-02-05 沈健 一种打弯部分倾斜的引线框架

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