CN201655790U - 一种铜铝线混合键合半导体芯片封装件 - Google Patents
一种铜铝线混合键合半导体芯片封装件 Download PDFInfo
- Publication number
- CN201655790U CN201655790U CN2010201712142U CN201020171214U CN201655790U CN 201655790 U CN201655790 U CN 201655790U CN 2010201712142 U CN2010201712142 U CN 2010201712142U CN 201020171214 U CN201020171214 U CN 201020171214U CN 201655790 U CN201655790 U CN 201655790U
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- copper
- wire
- pad
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/495—Material
- H01L2224/49505—Connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
本实用新型公开了一种铜铝线混合键合半导体芯片封装件,包括引线框架载体、半导体芯片、内引脚、金属丝和塑封体,所述半导体芯片上设置有大焊盘和小焊盘,所述金属丝为铝丝和铜丝,铝丝的一端与大焊盘电连接,另一端与内引脚电连接;铜丝的一端与小焊盘电连接,另一端与内引脚电连接;所述塑封体覆盖引线框架载体、半导体芯片、铝丝、铜丝和部分内引脚。本实用新型的结构简单合理,铝线键合芯片大焊盘满足大电流要求,而铜线键合芯片小焊盘避免产生键合短路,有效地降低了成本,产品质量稳定可靠,应用范围广。
Description
技术领域
本实用新型涉及电子信息自动化元器件制造技术领域,尤其涉及到一种铜铝线混合键合半导体芯片封装件。
背景技术
目前大功率半导体芯片主要采用铝线键合封装,而铜线键合技术主要用于中小功率半导体芯片的键合封装。若全部采用铜线线键合,由于铜线不适合粗线键合,因此若以一条铝线可完成的焊线(如:380um),改以铜线(如:50um)替代,约需15根左右的铜线。而实际大多数芯片焊盘是不能压15根铜线的;即使芯片焊盘能够满足,而生产速率会变慢很多。而若全部采用铝线键合,正常的铝线键合方法是先对芯片键合细铝线,再键合粗铝线,其具有以下几项缺点:一是因焊盘较小,铝线键合焊点大,制程条件因接近临界条件而难以控制,容易产生键合短路问题,使生产过程不良率过高,且影响产品的质量和可靠性;二是生产设备投入成本约为键合铜线的生产设备投入成本的三倍;三是生产速率慢,其中以粗铝线键合大焊盘的压线操作虽然比铜线快,但进行小焊盘的压线操作却比铜线慢3~5倍,故综合而言,整体的生产速度仍慢;四是芯片的焊盘(PAD)设计要很大,这样的要求给芯片制造增加了成本,在芯片制造成本与性价比激烈竞争的状况下,让芯片制造商的改进可能性很小。
发明内容
本实用新型的发明目的是克服现有技术的不足,解决铝线键合在半导体芯片焊盘上键合短路问题以及存在的质量和可靠性隐患,从而提供一种能避免产生键合短路、简单易行的一种铜铝线混合键合半导体芯片封装件。
本实用新型采用下述技术手段解决其技术问题:
一种铜铝线混合键合半导体芯片封装件,包括引线框架载体、半导体芯片、内引脚、金属丝和塑封体,所述半导体芯片上设置有大焊盘和小焊盘,所述金属丝为铝丝和铜丝,铝丝的一端与大焊盘电连接,另一端与内引脚电连接;铜丝的一端与小焊盘电连接,另一端与内引脚电连接;所述塑封体覆盖引线框架载体、半导体芯片、铝丝、铜丝和部分内引脚。
本实用新型与现有技术相比具有以下优点:
1、本实用新型采用铜铝线混合键合半导体芯片封装件,其结构简单合理,铝线键合芯片大焊盘满足大电流要求,而铜线键合芯片小焊盘避免产生键合短路,这解决了芯片焊接铝线容易短路问题,提高了产品的质量和可靠性;
2、本实用新型比原芯片封装压铝线的生产速度可提升约3~5倍,降低生产成本;
3、本实用新型减少了芯片上焊盘的面积,从而减少芯片用料,降低了芯片的单位生产成本。
附图说明
图1为现有铝线键合产品结构剖面示意图;
图2为本实用新型铜铝线混合键合半导体芯片封装件的结构剖面示意图;
图3为图2的俯视图。
图中标记为:
1—引线框架载体、2—粘片胶、3—半导体芯片、4—大焊盘、5—小焊盘、6—内引脚、7—塑封体、8—铝球、9—铝丝、10—铝焊点、11—铜球、12—铜丝、13—铜焊点。
具体实施方式
下面结合附图对本实用新型做进一步详细叙述:
图1所示为现有铝线键合产品结构剖面示意图,其因焊盘较小,铝线键合焊点大,容易产生键合短路问题,产品的质量和可靠性差,生产设备投入成本高,生产速率慢。图2、图3为本实用新型铜铝线混合键合半导体芯片封装件的结构示意图,其包括引线框架载体1、半导体芯片3、内引脚6、金属丝和塑封体7。所述半导体芯片3用粘片胶2粘接在引线框架载体1上,所述半导体芯片3上设置有大焊盘4和小焊盘5,在小焊盘5上打铜键合球11,使其铜丝12的一端与小焊盘5电连接,铜丝12的另一端与通过打铜焊点13与内引脚6电连接。在大焊盘4上打铝键合球8,使铝丝9的一端与大焊盘4电连接,铝丝9的另一端通过打铝焊点10与内引脚6电连接。所述塑封体7覆盖半导体芯片3、小焊盘5上的铜球11、铜丝12在内引脚6上的铜焊点13、大焊盘4上的铝球8、铝丝9在内引脚6上的铝焊点10、以及引线框架载体1和部分内引脚6,构成器件的整体,并对器件起到了保护和支撑作用。
本实用新型是铜铝线混合键合半导体芯片封装件结构,其综合了铜线键合芯片小焊盘的优点和粗铝线熔断电流大的优点,克服了铜线熔断电流小不能满足芯片大电流封装要求和铝线需要芯片设计大焊盘的缺点,解决了芯片焊接铝线容易短路问题,降低了生产成本,并给予芯片制造进一步改进余地。
Claims (1)
1.一种铜铝线混合键合半导体芯片封装件,包括引线框架载体(1)、半导体芯片(3)、内引脚(6)、金属丝和塑封体(7),其特征在于:所述半导体芯片(3)上设置有大焊盘(4)和小焊盘(5),所述金属丝为铝丝(9)和铜丝(12),铝丝(9)的一端与大焊盘(4)电连接,另一端与内引脚(6)电连接;铜丝(12)的一端与小焊盘(5)电连接,另一端与内引脚(6)电连接;所述塑封体(7)覆盖引线框架载体(1)、半导体芯片(3)、铝丝(9)、铜丝(12)和部分内引脚(6)。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010201712142U CN201655790U (zh) | 2010-04-17 | 2010-04-17 | 一种铜铝线混合键合半导体芯片封装件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010201712142U CN201655790U (zh) | 2010-04-17 | 2010-04-17 | 一种铜铝线混合键合半导体芯片封装件 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN201655790U true CN201655790U (zh) | 2010-11-24 |
Family
ID=43121034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010201712142U Expired - Fee Related CN201655790U (zh) | 2010-04-17 | 2010-04-17 | 一种铜铝线混合键合半导体芯片封装件 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN201655790U (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109887850A (zh) * | 2019-02-18 | 2019-06-14 | 长江存储科技有限责任公司 | 一种3d封装多点焊接的方法及装置、设备及存储介质 |
CN114005764A (zh) * | 2021-11-03 | 2022-02-01 | 湖州东科电子石英股份有限公司 | 一种芯片mos管导线焊接方法 |
WO2022151676A1 (zh) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | 芯片结构、封装结构及其制作方法 |
-
2010
- 2010-04-17 CN CN2010201712142U patent/CN201655790U/zh not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109887850A (zh) * | 2019-02-18 | 2019-06-14 | 长江存储科技有限责任公司 | 一种3d封装多点焊接的方法及装置、设备及存储介质 |
CN109887850B (zh) * | 2019-02-18 | 2021-10-01 | 长江存储科技有限责任公司 | 一种3d封装多点焊接的方法及装置、设备及存储介质 |
WO2022151676A1 (zh) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | 芯片结构、封装结构及其制作方法 |
CN114005764A (zh) * | 2021-11-03 | 2022-02-01 | 湖州东科电子石英股份有限公司 | 一种芯片mos管导线焊接方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101626008A (zh) | 一种铜线键合ic芯片封装件的生产方法 | |
CN201655790U (zh) | 一种铜铝线混合键合半导体芯片封装件 | |
CN207269022U (zh) | 一种引线框架及其芯片倒装封装结构 | |
CN201435388Y (zh) | 一种用于mosfet封装的引线框架 | |
CN107146777A (zh) | 一种免切割封装结构及其制造工艺 | |
CN207637785U (zh) | 新型高频微波大功率限幅器焊接组装结构 | |
CN100585821C (zh) | 一种用于金属框架的引线键合方法 | |
CN202050364U (zh) | 桥式整流器 | |
CN201527969U (zh) | 集成电路封装中引线框及基岛结构 | |
CN110648991B (zh) | 一种用于框架封装芯片的转接板键合结构及其加工方法 | |
CN203085519U (zh) | 一种芯片引线框架 | |
CN210245488U (zh) | 非接触式上下芯片封装结构 | |
CN201732781U (zh) | 一种引线框架 | |
CN202111082U (zh) | 多圈排列ic芯片封装件 | |
CN207637789U (zh) | 三片式内置电容式同步整流二极管 | |
CN213878074U (zh) | 一种引线键合工艺用基板 | |
CN203481210U (zh) | 一种基于框架采用点胶技术的扁平封装件 | |
CN201527975U (zh) | 一种铜线结构的功率晶体管 | |
CN217883965U (zh) | 一种适用于u盘的闪存封装结构 | |
CN202111073U (zh) | 集成电路的高低焊线结构 | |
CN219778887U (zh) | 一种散热叠塑封体封装结构 | |
CN201402805Y (zh) | 一种铜线键合ic芯片封装件 | |
CN103400811A (zh) | 一种基于框架采用特殊点胶技术的扁平封装件及其制作工艺 | |
CN203339152U (zh) | 一种基于冲压框架的单芯片扁平封装件 | |
CN202178252U (zh) | 多圈排列无载体双ic芯片封装件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
DD01 | Delivery of document by public notice |
Addressee: Sichuan Dayan Electronics Co., Ltd. Document name: Notification to Pay the Fees |
|
DD01 | Delivery of document by public notice |
Addressee: Sichuan Dayan Electronics Co., Ltd. Document name: Notification of Termination of Patent Right |
|
DD01 | Delivery of document by public notice | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101124 Termination date: 20160417 |
|
CF01 | Termination of patent right due to non-payment of annual fee |