CN202111073U - 集成电路的高低焊线结构 - Google Patents

集成电路的高低焊线结构 Download PDF

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Publication number
CN202111073U
CN202111073U CN2011202411236U CN201120241123U CN202111073U CN 202111073 U CN202111073 U CN 202111073U CN 2011202411236 U CN2011202411236 U CN 2011202411236U CN 201120241123 U CN201120241123 U CN 201120241123U CN 202111073 U CN202111073 U CN 202111073U
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China
Prior art keywords
bonding wire
integrated circuit
bonding wires
wire structure
adjacent
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Expired - Lifetime
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CN2011202411236U
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张建国
伍江涛
左福平
张航
龚道发
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Shenzhen Diantong Wintronic Microelectronics Co Ltd
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Shenzhen Diantong Wintronic Microelectronics Co Ltd
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Priority to CN2011202411236U priority Critical patent/CN202111073U/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Wire Bonding (AREA)

Abstract

本实用新型的集成电路的高低焊线结构，技术目的是提供一种焊线处于不同一水平面、进而提升产品合格率的集成电路的高低焊线结构。包括有塑封体，在所述塑封体中设有基岛，所述基岛上设有半导体芯片，在所述半导体芯片上设有焊线，焊线连接有引脚，所述相邻两条焊线之间呈错开结构，两条焊线处于非同一水平面。相邻两条焊线之间呈错开结构可以减小塑封工序冲丝的危险，避免以上情况引起的产品失效，提升了产品合格率，适用于集成电路的生产领域。

Description

集成电路的高低焊线结构
技术领域
本实用新型涉及一种集成电路，更具体的说，涉及一种集成电路的高低焊线结构。
背景技术
半导体封装日趋集成化、多功能化、小型化。这样标志现代化工业生产中技术越来越成熟，使得在半导体封装技术要求越来越高，并且越来越难。有些芯片封装功能简单，且浪费空间，耗时相对较长，因此封装结构也需要不断的优化。现有技术中的集成电路焊线设计基本是在同一平面上，这种结构设计存在的技术缺陷是焊线与焊线的密度高，容易产出不良产品，导致产品合格率降低。
发明内容
本实用新型的技术目的是克服现有技术中集成电路芯片存在着焊线集中一水平面，产品合格率降低的技术问题，提供一种焊线处于不同一水平面、进而提升产品合格率的集成电路的高低焊线结构。
为实现以上技术目的，本实用新型的技术方案是：
集成电路的高低焊线结构，包括有塑封体，在所述塑封体中设有基岛，所述基岛上设有半导体芯片，在所述半导体芯片上设有焊线，焊线连接有引脚，其特征是：所述相邻两条焊线之间呈错开结构，两条焊线处于非同一水平面。
更进一步的，所述相邻两条焊线之间相距为至少两倍线径距离。
相邻两条焊线之间呈错开结构，可以满足集成化、多功能、小型化要求。这样的结构设计使得不合理的芯片焊点结构得以运用，降低了产出不良品的风险，大大增加了产品可靠性，节约人工，缩短了生产周期，降低了设备的投入，便于管理和节约成本。本相邻两条焊线之间呈错开结构可以满足最佳的性能和最低的成本设计。缩短生产周期，这种新型相邻两条焊线之间呈错开结构可以时芯片体积做得较小，也解决芯片焊点位置分布不合理的情况，减小芯片生产难度。大大增加产品可靠性，这种新型相邻两条焊线之间呈错开结构可以解决键合引线间距离太小或短路的问题，这种新型相邻两条焊线之间呈错开结构还可以减小塑封工序冲丝的危险，避免以上情况引起的产品失效，提升了产品合格率。
附图说明
图1是本实用新型一个实施例的结构示意图。
具体实施方式
结合图1，详细说明本实用新型的具体实施方式
集成电路的高低焊线结构，包括有塑封体1，在所述塑封体中设有基岛2，所述基岛2上设有半导体芯片3，在所述半导体芯片3上设有焊线4，焊线4连接有引脚5，所述相邻两条焊线4之间呈错开结构，两条焊线处于非同一水平面。所述相邻两条焊线之间相距为至少两倍线径距离。
相邻两条焊线4之间呈错开结构，可以满足集成化、多功能、小型化要求。这样的结构设计使得不合理的芯片焊点结构得以运用，降低了产出不良品的风险，大大增加了产品可靠性，节约人工，缩短了生产周期，降低了设备的投入，便于管理和节约成本。

Claims (2)

1.集成电路的高低焊线结构，包括有塑封体，在所述塑封体中设有基岛，所述基岛上设有半导体芯片，在所述半导体芯片上设有焊线，焊线连接有引脚，其特征是：所述相邻两条焊线之间呈错开结构，两条焊线处于非同一水平面。
2.根据权利要求1所述的集成电路的高低焊线结构，其特征是：所述相邻两条焊线之间相距为至少两倍线径距离。
CN2011202411236U 2011-07-08 2011-07-08 集成电路的高低焊线结构 Expired - Lifetime CN202111073U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321140A (zh) * 2018-01-17 2018-07-24 江苏海德半导体有限公司 一种芯片封装超声波焊接工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108321140A (zh) * 2018-01-17 2018-07-24 江苏海德半导体有限公司 一种芯片封装超声波焊接工艺
CN108321140B (zh) * 2018-01-17 2019-11-05 江苏海德半导体有限公司 一种芯片封装超声波焊接工艺

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