CN202871779U - 防塌丝多芯片集成电路引线框架 - Google Patents

防塌丝多芯片集成电路引线框架 Download PDF

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Publication number
CN202871779U
CN202871779U CN2012205707301U CN201220570730U CN202871779U CN 202871779 U CN202871779 U CN 202871779U CN 2012205707301 U CN2012205707301 U CN 2012205707301U CN 201220570730 U CN201220570730 U CN 201220570730U CN 202871779 U CN202871779 U CN 202871779U
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China
Prior art keywords
lead frame
base island
wire
integrated circuit
chip integrated
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Expired - Fee Related
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CN2012205707301U
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English (en)
Inventor
吴志勇
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JIANGYIN SUNNY ORIENT TECHNOLOGY Co Ltd
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JIANGYIN SUNNY ORIENT TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型涉及一种防塌丝多芯片集成电路引线框架，它包括第一基岛（1）、第二基岛（2）以及多个内引脚（3），其特征在于所述第一基岛（1）的左半部向下延伸，所述第二基岛（2）的右半部向上延伸，所述第一基岛（1）向下延伸的部分与第二基岛（2）向上延伸的部分错位布置。本实用新型通过第一基岛以及第二基岛结构的变化，可以减少粘贴在其表面芯片间的距离，减小连接引线的长度，从而使得在作业过程中不容易出现塌丝现象，降低了作业的难度，产品可靠性较高。

Description

防塌丝多芯片集成电路引线框架
技术领域
本实用新型涉及一种防塌丝多芯片集成电路引线框架，属于半导体封装行业。
背景技术
如图1所示，传统的多芯片集成电路引线框架包括第一基岛1、第二基岛2以及多个内引脚5，第一基岛1用于粘贴第一芯片3，第二基岛2用于粘贴第二芯片4，第一芯片3与第二芯片之间的连接引线6非常长，在作业过程中容易出现塌丝现象，增加了作业的难度，且其破断力远远低于其他连接引线，对产品的质量及可靠性存在潜在风险。因此寻求一种产品可靠性较高，降低作业难度的防塌丝多芯片集成电路引线框架尤为重要。
发明内容
本实用新型的目的在于克服上述不足，提供一种防塌丝多芯片集成电路引线框架，使得产品可靠性较高，降低作业难度。 
本实用新型的目的是这样实现的：
一种防塌丝多芯片集成电路引线框架，它包括第一基岛、第二基岛以及多个内引脚，所述第一基岛的左半部向下延伸，所述第二基岛的右半部向上延伸，所述第一基岛向下延伸的部分与第二基岛向上延伸的部分错位布置。
与现有技术相比，本实用新型的有益效果是：
本实用新型通过第一基岛以及第二基岛结构的变化，可以减少粘贴在其表面芯片间的距离，减小连接引线的长度，从而使得在作业过程中不容易出现塌丝现象，降低了作业的难度，产品可靠性较高。
附图说明
图1为传统多芯片集成电路引线框架的结构示意图。
图2为本实用新型防塌丝多芯片集成电路引线框架的结构示意图。
其中：
第一基岛1
第二基岛2
第一芯片3
第二芯片4
内引脚5
连接引线6。
具体实施方式
参见图2，本实用新型涉及的一种防塌丝多芯片集成电路引线框架，它包括第一基岛1、第二基岛2以及多个内引脚3，所述第一基岛1用于粘贴第一芯片3，所述第二基岛2用于粘贴第二芯片4，所述第一基岛1的左半部向下延伸，所述第二基岛2的右半部向上延伸，所述第一基岛1向下延伸的部分与第二基岛2向上延伸的部分错位布置。
由于第一基岛1用于粘贴第一芯片3，且方向为竖放，故可以将其左半部往下延伸，延伸后将减少第一芯片3与第二芯片4之间的距离，从而减小连接引线6的长度，使生产更稳定可靠；由于第二基岛右部分为空白无利用区域，故可将第二基岛往上延伸，一方面可以缩短两芯片间的距离，尤其重要的是大大的增加了MOS管（金属—绝缘体—半导体）的散热面积。

Claims (1)

1.一种防塌丝多芯片集成电路引线框架，它包括第一基岛（1）、第二基岛（2）以及多个内引脚（3），其特征在于所述第一基岛（1）的左半部向下延伸，所述第二基岛（2）的右半部向上延伸，所述第一基岛（1）向下延伸的部分与第二基岛（2）向上延伸的部分错位布置。
CN2012205707301U 2012-11-01 2012-11-01 防塌丝多芯片集成电路引线框架 Expired - Fee Related CN202871779U (zh)

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Granted publication date: 20130410

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