CN202352658U - 一种新的半导体封装引线框架 - Google Patents

一种新的半导体封装引线框架 Download PDF

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Publication number
CN202352658U
CN202352658U CN 201120498441 CN201120498441U CN202352658U CN 202352658 U CN202352658 U CN 202352658U CN 201120498441 CN201120498441 CN 201120498441 CN 201120498441 U CN201120498441 U CN 201120498441U CN 202352658 U CN202352658 U CN 202352658U
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China
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lead frame
pad
semiconductor packaging
novel semiconductor
frame
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Expired - Fee Related
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CN 201120498441
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English (en)
Inventor
金铉东
张才良
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ZHENGWEN ELECTRONICS (SUZHOU) CO Ltd
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ZHENGWEN ELECTRONICS (SUZHOU) CO Ltd
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Priority to CN 201120498441 priority Critical patent/CN202352658U/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型涉及一种新的半导体封装引线框架，包括框架基板、围绕所述框架基板周围排列的若干引脚，其特征在于，在所述的框架基板上设置有分别固定支撑两个芯片的第一垫片和第二垫片。本实用新型考虑了封装使用不同的芯片尺寸大小，使其减少了原材的浪费，而且其结构简单，具有合理、性能稳定的特点。

Description

一种新的半导体封装引线框架
技术领域
本实用新型涉及一种半导体封装技术,更具体的涉及一种新的半导体封装引线框架。
背景技术
在现有的半导体封装技术中，采用的是只有单一的用于固定支撑芯片部位的引线框架，很难有方法来封装两个独立的芯片模式的产品，两个芯片置于同一垫片部位上，不采用一定的措施就很容易造成短路现象，不良率问题偏高。
实用新型内容
 本实用新型的目的是解决上述缺陷，提供了一种半导体封装引线框架，其具有结构简单，合理，性能稳定等优点。
本实用新型的内容是：一种新的半导体封装引线框架，包括框架基板、围绕所述框架基板周围排列的若干引脚，其特征在于，在所述的框架基板上设置有分别固定支撑两个芯片的第一垫片和第二垫片。
所述第一垫片与第二垫片之间的距离是0.2mm～0.5mm。
所述基板与所述引脚是通过引线电性连接的，每相邻所述引线无交叉。
与现有技术相比，本实用新型具有以下优点：本实用新型的引线框架在设计时，考虑了封装使用不同的芯片尺寸大小，设计了两片不同大小用于固定支撑芯片的部位，很好的避免了短路现象的发生，而且封装时减少了其它一些原材的使用，如引线框架自身原料使用量和引线连接的使用量，达到了节省的目的。
附图说明
图1是本实用新型的结构示意图。
具体实施方式
下面结合附图对本实用新型作进一步的详细说明。
参照图1所示，包括框架基板、围绕框架基板周围排列的若干引脚1，在框架基板上设置有分别固定支撑两个芯片的第一垫片11和第二垫片12，能很好的避免了短路现象的发生，而且还减少了金线等原材的使用，而且第一垫片11与第二垫片12之间的距离是0.2mm～0.5mm，基板与引脚1是引线2电性连接的，每相邻引线2无交叉。
   本发明的目的给出了对本发明优选实施例的描述，可以使本领域的技术人员更全面地理解本发明，但不以任何方式限制本发明，而且任何可以对本发明进行修改或者等同替换，均应涵盖在本发明专利的保护范围内。

Claims (3)

1.一种新的半导体封装引线框架，包括框架基板、围绕所述框架基板周围排列的若干引脚，其特征在于，在所述的框架基板上设置有分别固定支撑两个芯片的第一垫片和第二垫片。
2.如权利要求1所述的一种新的半导体封装引线框架，其特征在于，所述第一垫片与第二垫片之间的距离是0.2mm～0.5mm。
3.如权利要求1所述的一种新的半导体封装引线框架，其特征在于，所述基板与所述引脚是通过引线电性连接的，每相邻所述引线无交叉。
CN 201120498441 2011-12-05 2011-12-05 一种新的半导体封装引线框架 Expired - Fee Related CN202352658U (zh)

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CN 201120498441 CN202352658U (zh) 2011-12-05 2011-12-05 一种新的半导体封装引线框架

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465423A (zh) * 2014-12-08 2015-03-25 杰群电子科技（东莞）有限公司 一种双引线框架叠合设计半导体器件封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465423A (zh) * 2014-12-08 2015-03-25 杰群电子科技（东莞）有限公司 一种双引线框架叠合设计半导体器件封装方法
CN104465423B (zh) * 2014-12-08 2017-08-22 杰群电子科技（东莞）有限公司 一种双引线框架叠合设计半导体器件封装方法

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Granted publication date: 20120725

Termination date: 20131205