CN102437134A - 一种超小型封装体及其制作方法 - Google Patents

一种超小型封装体及其制作方法 Download PDF

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CN102437134A
CN102437134A CN2011104015568A CN201110401556A CN102437134A CN 102437134 A CN102437134 A CN 102437134A CN 2011104015568 A CN2011104015568 A CN 2011104015568A CN 201110401556 A CN201110401556 A CN 201110401556A CN 102437134 A CN102437134 A CN 102437134A
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back electrode
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CN102437134B (zh
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高洪涛
张江元
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Reach Technology (chengdu) Co Ltd
Shanghai Kaihong Sci & Tech Electronic Co Ltd
Shanghai Kaihong Electronic Co Ltd
Diodes Technology Chengdu Co Ltd
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Reach Technology (chengdu) Co Ltd
Shanghai Kaihong Sci & Tech Electronic Co Ltd
Shanghai Kaihong Electronic Co Ltd
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Abstract

本发明提供了一种超小型封装体及其制作方法。所述超小型封装体，包括芯片、设置于芯片背面的一片式背电极、以及设置于芯片正面的多个片式正电极，所述片式背电极具有一突出芯片侧边的端部，所述多个片式正电极亦各自具有一突出芯片侧边的端部。本发明的优点在于，采用的片式背电极以及片式正电极都是贴在芯片的表面，并直接采用片式露出的端部作为封装体的引脚，故芯片外围的电学连接引线仅仅占用了很少的体积。本发明所提供的技术方案在芯片的体积一定的情况下，降低了封装体的总体积，故可以适用于小型甚至超小型芯片的封装。

Description

一种超小型封装体及其制作方法
技术领域
本发明涉及半导体封装领域，尤其涉及一种超小型封装体及其制作方法。
背景技术
半导体器件有越来越小型化的发展趋势，为了尽量减少完成封装后的半导体器件的体积，就应该尽量增大芯片在完成封装后的半导体器件中所占的体积比。在传统的完成封装后的半导体器件中芯片被贴装在引线框架的支撑平台上，再由引线将芯片的另外一些电极连接到焊线台上，在这种器件中焊线台以及支撑芯片的引线框架将会占据大量的体积，因此芯片在整个半导体器件中所占的体积比不可能太高。这些因素制约了半导体器件的小型化发展趋势，例如附图1所示是是现有的一种超小型QFN封装体的示意图，包括芯片10、芯片贴装部11以及引脚12。采用这种结构的封装体尺寸通常为0.62mm×0.32mm，但芯片10的尺寸大约为0.2mm×0.2mm，大部分空间被芯片贴装部11以及引脚12占据，芯片10只占大约20％的面积。随着芯片10的尺寸的减少，上述比例还会进一步减少，因为贴装部11以及引脚12的尺寸是有极限的，其所占比例会相对增多。
发明内容
本发明所要解决的技术问题是，提供一种超小型封装体及其制作方法，能够提高芯片在封装体中所占体积的比例，从而降低封装体的体积。
为了解决上述问题，本发明提供了一种超小型封装体，包括芯片、设置于芯片背面的一片式背电极、以及设置于芯片正面的多个片式正电极，所述片式背电极具有一突出芯片侧边的端部，所述多个片式正电极亦各自具有一突出芯片侧边的端部。
作为可选的技术方案，所述片式背电极的突出芯片侧边的端部与多个片式正电极的突出芯片侧边的端部设置于芯片的同一侧边。
作为可选的技术方案，所述片式背电极的突出芯片侧边的端部芯片的一侧边，所述多个片式正电极的突出芯片侧边的端部设置于与芯片上述侧边相对的另一侧边。
作为可选的技术方案，进一步包括一塑封体，所述塑封体包裹所述芯片、片式背电极以及多个片式正电极，并暴露出片式背电极的突出芯片侧边的端部，以及暴露出所述多个片式正电极的突出芯片侧边的端部。
本发明进一步提供了一种上述封装体的制作方法，包括如下步骤：提供片式背电极；将芯片的背面贴装在片式背电极的表面，使芯片的背面与片式背电极电学导通，并使片式背电极具有一突出芯片侧边的端部；将多个片式正电极贴装在芯片的正面，遵照预先设计使每个片式正电极均与对应的芯片表面的焊盘电学导通，并使所述多个片式正电极各自具有一突出芯片侧边的端部。
作为可选的技术方案，在贴装多个片式正电极的步骤中，使所述片式背电极的突出芯片侧边的端部与多个片式正电极的突出芯片侧边的端部设置于芯片的同一侧边。
作为可选的技术方案，在贴装多个片式正电极的步骤中，使所述片式背电极的突出芯片侧边的端部芯片的一侧边，所述多个片式正电极的突出芯片侧边的端部设置于与芯片上述侧边相对的另一侧边。
根据权利要求5所述的制作方法，其特征在于，其特征在于，在贴装多个片式正电极的步骤之后，进一步包括如下步骤：形成一塑包裹所述芯片、片式背电极以及多个片式正电极的塑封体，并暴露出片式背电极的突出芯片侧边的端部，以及暴露出所述多个片式正电极的突出芯片侧边的端部。
本发明的优点在于，采用的片式背电极以及片式正电极都是贴在芯片的表面，并直接采用片式露出的端部作为封装体的引脚，故芯片外围的电学连接引线仅仅占用了很少的体积。本发明所提供的技术方案在芯片的体积一定的情况下，降低了封装体的总体积，故可以适用于小型甚至超小型芯片的封装。
附图说明
附图1所示是是现有的一种超小型QFN封装体的示意图；
附图2所示是本发明的第一具体实施方式中封装体制作方法的实施步骤示意图；
附图3A至附图3E所示是本发明的第一具体实施方式中所述步骤的工艺示意图；
附图4所示是本发明的第二具体实施方式中封装体制作方法的实施步骤示意图；
附图5A与附图5B所示是本发明的第二具体实施方式中所述步骤的工艺示意图。
具体实施方式
下面结合附图对本发明提供的一种超小型封装体及其制作方法的具体实施方式做详细说明。
首先结合附图给出本发明一种超小型封装体及其制作方法的第一具体实施方式。
附图2所示是本发明的第一具体实施方式中封装体制作方法的实施步骤示意图，包括如下步骤：步骤S10，提供片式背电极；步骤S11，将芯片的背面贴装在片式背电极的表面；步骤S12，将一片式正电极贴装在芯片的正面；步骤S13，形成一塑封体。
附图3A至附图3E所示是本具体实施方式中所述步骤的工艺示意图，采用立体图的形式对上述工艺进行具体说明。
附图3A所示，参考步骤S10，提供片式背电极110，所述片式背电极110可以是任何一种用金属材料制作的片式结构。
附图3B所示，参考步骤S11，将芯片100的背面贴装在片式背电极110的表面。本步骤可以采用导电焊料焊接的方法或者采用导电胶粘贴等方法，使芯片100的背面与片式背电极110电学导通。本步骤进一步需要片式背电极110具有一突出芯片100侧边的端部111，该端部111用于形成最终封装体的引出电极。既然芯片100已经用于封装，则显然所述芯片100应当是已经制作有半导体器件的，故芯片100的正面应当是制作半导体器件的一面，芯片100的正面具有一个焊盘101，背面是与正面相对的另一面，本具体实施方式所述的芯片100的背面进一步具有背电极的作用。
附图3C所示，参考步骤S12，将一片式正电极120贴装在芯片100的正面。本实施方式中，芯片100的正面仅具有一个焊盘101，故应当将片式正电极120与焊盘101电学导通，贴装可以采用导电焊料焊接的方法或者采用导电胶粘贴等方法。并且片式正电极120进一步具有一突出芯片100侧边的端部121，该端部121用于形成最终封装体的引出电极。在本具体实施方式中，所述片式背电极110的突出芯片100侧边的端部111与片式正电极120的突出芯片100侧边的端部121设置于芯片100的同一侧边。
附图3D所示是步骤S12的实施完毕的另一种可能的状态，在附图3D中，所述片式背电极110的端部111设置芯片100的一侧边，而片式正电极120的端部121设置于芯片100与上述侧边相对的另一侧边。
以上附图3C与3D中，芯片100的形状均为矩形，这是最为常见的形状。如果芯片110的形状是其他的特殊形状，本领域内技术人员可以根据上述内容以及附图3C和附图3D所揭露的技术构思来重新布置两端部的位置关系。
在其他的实施方式中，如果芯片100的正面具有多个焊盘，则应当提供多个片式正电极，并遵照预先设计使每个片式正电极均与对应的芯片表面的焊盘电学导通，并使多个片式正电极各自具有一突出芯片侧边的端部。
从附图3C和附图3D中可以看出，片式背电极110以及片式正电极120实质上已经形成了对芯片100背面和正面的密封结构，而在这种结构中，由于两个电极都是贴在芯片100的表面，故芯片100占去了封装体的大部分体积，从而在芯片100的体积一定的情况下，降低了封装体的总体积，故可以适用于小型甚至超小型芯片的封装。
附图3E所示，参考步骤S13，形成一塑封体130。所述塑封体130包裹所述芯片100、片式背电极110以及片式正电极120，并暴露出片式背电极110的端部111和片式正电极120的端部121。本步骤为可选步骤。对于附图3C和附图3D的结构而言，实质上已经形成了对芯片100正面和背面的密封结构，可以直接应用在PCB等场合。本步骤进一步形成了一塑封体130，可以进一步提高封装体抵抗外界环境干扰的能力。
附图4所示是本发明的第二具体实施方式中封装体制作方法的实施步骤示意图，包括如下步骤：步骤S20，提供片式背电极；步骤S21，将芯片的背面贴装在片式背电极的表面；步骤S22，将两个片式正电极贴装在芯片的正面。
本实施方式的步骤S20和步骤S21与前一个具体实施方式类似，此处不再赘述。
本实施方式是针对芯片正面具有多个焊盘，需要引出两个或者多个电极的情况，故本具体实施方式中的步骤S22是将两个片式正电极贴装在芯片的正面。为了更清楚的说明步骤S22，接下来的附图5A和附图5B采用立体图的形式对上述步骤进行说明。
附图5A是步骤S21实施完毕后的封装体立体结构图，包括芯片200、片式背电极210，芯片200的正面具有焊盘201和202。继续实施步骤S22，参考附图5B是步骤S22实施完毕后的封装体立体结构图，两个片式正电极221与222被贴装在芯片的正面。片式背电极210的突出芯片200侧边的端部与片式正电极221与222的突出芯片200侧边的端部设置于芯片200的同一侧边上。上述三个突出的端部将作为封装体中的芯片200与外界形成电学连接的电极。
同前一个具体实施方式类似的，附图5B所示的结构可以直接应用在PCB等场合，也可以再实施一塑封的步骤以提高其可靠性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (8)

1.一种超小型封装体，其特征在于，包括芯片、设置于芯片背面的一片式背电极、以及设置于芯片正面的多个片式正电极，所述片式背电极具有一突出芯片侧边的端部，所述多个片式正电极亦各自具有一突出芯片侧边的端部。
2.根据权利要求1所述的超小型封装体，其特征在于，所述片式背电极的突出芯片侧边的端部与多个片式正电极的突出芯片侧边的端部设置于芯片的同一侧边。
3.根据权利要求1所述的超小型封装体，其特征在于，所述片式背电极的突出芯片侧边的端部芯片的一侧边，所述多个片式正电极的突出芯片侧边的端部设置于与芯片上述侧边相对的另一侧边。
4.根据权利要求1所述的超小型封装体，其特征在于，进一步包括一塑封体，所述塑封体包裹所述芯片、片式背电极以及多个片式正电极，并暴露出片式背电极的突出芯片侧边的端部，以及暴露出所述多个片式正电极的突出芯片侧边的端部。
5.一种权利要求1所述封装体的制作方法，其特征在于，包括如下步骤：
提供片式背电极；
将芯片的背面贴装在片式背电极的表面，使芯片的背面与片式背电极电学导通，并使片式背电极具有一突出芯片侧边的端部；
将多个片式正电极贴装在芯片的正面，遵照预先设计使每个片式正电极均与对应的芯片表面的焊盘电学导通，并使所述多个片式正电极各自具有一突出芯片侧边的端部。
6.根据权利要求5所述的制作方法，其特征在于，在贴装多个片式正电极的步骤中，使所述片式背电极的突出芯片侧边的端部与多个片式正电极的突出芯片侧边的端部设置于芯片的同一侧边。
7.根据权利要求5所述的制作方法，其特征在于，在贴装多个片式正电极的步骤中，使所述片式背电极的突出芯片侧边的端部芯片的一侧边，所述多个片式正电极的突出芯片侧边的端部设置于与芯片上述侧边相对的另一侧边。
8.根据权利要求5所述的制作方法，其特征在于，其特征在于，在贴装多个片式正电极的步骤之后，进一步包括如下步骤：
形成一塑包裹所述芯片、片式背电极以及多个片式正电极的塑封体，并暴露出片式背电极的突出芯片侧边的端部，以及暴露出所述多个片式正电极的突出芯片侧边的端部。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979306A (zh) * 2014-04-11 2015-10-14 万国半导体(开曼)股份有限公司 小尺寸贴片印迹面积的功率半导体器件及制备方法
CN111354703A (zh) * 2018-12-21 2020-06-30 深圳市泛宜微电子技术有限公司 一种封装电子元件及其制造方法
CN111354707A (zh) * 2018-12-21 2020-06-30 深圳市泛宜微电子技术有限公司 一种功率器件的封装模块及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9646920B2 (en) * 2014-06-07 2017-05-09 Alpha And Omega Semiconductor (Cayman), Ltd Power semiconductor device with small contact footprint and the preparation method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072240A (en) * 1998-10-16 2000-06-06 Denso Corporation Semiconductor chip package
US20060214171A1 (en) * 2005-02-14 2006-09-28 Kabushiki Kaisha Toshiba Semiconductor light-emitting element and light-emitting device
CN101740640A (zh) * 2009-12-18 2010-06-16 海湾电子(山东)有限公司 片状电极式二极管
WO2011021447A1 (ja) * 2009-08-19 2011-02-24 リンテック株式会社 発光シート及びその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072240A (en) * 1998-10-16 2000-06-06 Denso Corporation Semiconductor chip package
US20060214171A1 (en) * 2005-02-14 2006-09-28 Kabushiki Kaisha Toshiba Semiconductor light-emitting element and light-emitting device
WO2011021447A1 (ja) * 2009-08-19 2011-02-24 リンテック株式会社 発光シート及びその製造方法
CN101740640A (zh) * 2009-12-18 2010-06-16 海湾电子(山东)有限公司 片状电极式二极管

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104979306A (zh) * 2014-04-11 2015-10-14 万国半导体(开曼)股份有限公司 小尺寸贴片印迹面积的功率半导体器件及制备方法
CN104979306B (zh) * 2014-04-11 2018-06-01 万国半导体(开曼)股份有限公司 小尺寸贴片印迹面积的功率半导体器件及制备方法
CN111354703A (zh) * 2018-12-21 2020-06-30 深圳市泛宜微电子技术有限公司 一种封装电子元件及其制造方法
CN111354707A (zh) * 2018-12-21 2020-06-30 深圳市泛宜微电子技术有限公司 一种功率器件的封装模块及其制造方法

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