CN102364680A - Dip封装引线框架 - Google Patents

Dip封装引线框架 Download PDF

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Publication number
CN102364680A
CN102364680A CN2011103327312A CN201110332731A CN102364680A CN 102364680 A CN102364680 A CN 102364680A CN 2011103327312 A CN2011103327312 A CN 2011103327312A CN 201110332731 A CN201110332731 A CN 201110332731A CN 102364680 A CN102364680 A CN 102364680A
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CN
China
Prior art keywords
lead frame
lead
dip
dao
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011103327312A
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English (en)
Inventor
侯友良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WUXI RED MICROELECTRONICS CO Ltd
Original Assignee
WUXI RED MICROELECTRONICS CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WUXI RED MICROELECTRONICS CO Ltd filed Critical WUXI RED MICROELECTRONICS CO Ltd
Priority to CN2011103327312A priority Critical patent/CN102364680A/zh
Publication of CN102364680A publication Critical patent/CN102364680A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明提供了DIP封装引线框架，其使得封装的成本低、封装的稳定性好。其包括框架底板、基岛、外引脚，其特征在于：所述框架底板上设置有两个基岛，两块芯片分别封装于对应的基岛，两块所述芯片之间通过内引线连接，两块芯片分别通过内引线连接对应的所述外引脚。

Description

DIP封装引线框架
技术领域
    本发明涉及半导体器件封装的技术领域，具体为DIP封装引线框架。
背景技术
标准的DIP-8L封装型式的引线框架结构为单基岛，基岛上只能放置一只芯片，如需要由两种芯片组合时，现有的结构将其分别封装成两个器件，然后通过外部连线组合而成，由于需要分别封装两个器件，且需要外部连线连接，其封装的成本高，封装的稳定性差。
发明内容
针对上述问题，本发明提供了DIP封装引线框架，其使得封装的成本低、封装的稳定性好。
DIP封装引线框架，其技术方案是这样的：其包括框架底板、基岛、外引脚，其特征在于：所述框架底板上设置有两个基岛，两块芯片分别封装于对应的基岛，两块所述芯片之间通过内引线连接，两块芯片分别通过内引线连接对应的所述外引脚。
采用本发明的结构后，DIP-8L封装型式的引线框架的框架底板上设置有两个基岛，两块芯片分别封装于对应的基岛，芯片之间通过内引线连接，其封装的成本低，一次封装成型，且引线均为内引线，其封装的稳定性好。
附图说明
图1为本发明的DIP-8L封装引线框架结构示意图。
具体实施方式
见图1，其包括框架底板1、外引脚8，框架底板上设置有两个基岛2、3，两块芯片4、5分别封装于对应的基岛2、3，两块芯片4、5之间通过内引线6连接，两块芯片4、5分别通过内引线7连接对应的外引脚8。
DIP封装：双列直插式封装。

Claims (1)

1.DIP封装引线框架，其包括框架底板、基岛、外引脚，其特征在于：所述框架底板上设置有两个基岛，两块芯片分别封装于对应的基岛，两块所述芯片之间通过内引线连接，两块芯片分别通过内引线连接对应的所述外引脚。
CN2011103327312A 2011-10-28 2011-10-28 Dip封装引线框架 Pending CN102364680A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011103327312A CN102364680A (zh) 2011-10-28 2011-10-28 Dip封装引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011103327312A CN102364680A (zh) 2011-10-28 2011-10-28 Dip封装引线框架

Publications (1)

Publication Number Publication Date
CN102364680A true CN102364680A (zh) 2012-02-29

Family

ID=45691238

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103327312A Pending CN102364680A (zh) 2011-10-28 2011-10-28 Dip封装引线框架

Country Status (1)

Country Link
CN (1) CN102364680A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103337489A (zh) * 2013-07-12 2013-10-02 无锡红光微电子有限公司 一种sop-8l封装引线框架
CN103811456A (zh) * 2014-02-18 2014-05-21 江阴苏阳电子股份有限公司 多芯片dip封装结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101834176A (zh) * 2010-04-26 2010-09-15 日银Imp微电子有限公司 一种半桥驱动电路芯片

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101834176A (zh) * 2010-04-26 2010-09-15 日银Imp微电子有限公司 一种半桥驱动电路芯片

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103337489A (zh) * 2013-07-12 2013-10-02 无锡红光微电子有限公司 一种sop-8l封装引线框架
CN103811456A (zh) * 2014-02-18 2014-05-21 江阴苏阳电子股份有限公司 多芯片dip封装结构

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Application publication date: 20120229