CN103337489A - 一种sop-8l封装引线框架 - Google Patents

一种sop-8l封装引线框架 Download PDF

Info

Publication number
CN103337489A
CN103337489A CN2013102914455A CN201310291445A CN103337489A CN 103337489 A CN103337489 A CN 103337489A CN 2013102914455 A CN2013102914455 A CN 2013102914455A CN 201310291445 A CN201310291445 A CN 201310291445A CN 103337489 A CN103337489 A CN 103337489A
Authority
CN
China
Prior art keywords
dao
sop
chip
chips
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2013102914455A
Other languages
English (en)
Inventor
侯友良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Red Microelectronics Co ltd
Original Assignee
Wuxi Red Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Red Microelectronics Co ltd filed Critical Wuxi Red Microelectronics Co ltd
Priority to CN2013102914455A priority Critical patent/CN103337489A/zh
Publication of CN103337489A publication Critical patent/CN103337489A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明提供了一种SOP-8L封装引线框架，其使得一个器件内能够同时封装两个相关联芯片，无需外部连线，使得性能稳定，且使得产品芯片的封装小型化、微型化得以实现，一个器件同时也降低了成本。其包括框架、基岛、外引脚，所述框架的中心位置设置有基岛，所述框架的其中一对侧分别设置有外引脚，其特征在于：所述框架的中心位置设置有两个基岛，装于所述基岛上的芯片通过内引线分别连接对应的外引脚。

Description

一种SOP-8L封装引线框架
技术领域
    本发明涉及半导体封装的技术领域，具体为一种SOP-8L封装引线框架。
背景技术
标准的SOP-8L封装型式的引线框架为单基岛，其基岛的中心位置放置有一个芯片，但是，伴随着产品的不断复杂化，现有的产品出现了同时关联两个芯片的情况，现有的封装结构只能分别封装成两个器件，再通过外部连线组成，由于使用了外部连线，使得性能稳定性差；且由于使用了两个封装器件，其使得产品的芯片封装体积大，且增加了成本。
发明内容
针对上述问题，本发明提供了一种SOP-8L封装引线框架，其使得一个器件内能够同时封装两个相关联芯片，无需外部连线，使得性能稳定，且使得产品芯片的封装小型化、微型化得以实现，一个器件同时也降低了成本。
一种SOP-8L封装引线框架，其技术方案是这样的：其包括框架、基岛、外引脚，所述框架的中心位置设置有基岛，所述框架的其中一对侧分别设置有外引脚，其特征在于：所述框架的中心位置设置有两个基岛，装于所述基岛上的芯片通过内引线分别连接对应的外引脚。
其进一步特征在于：所述框架的其中一对侧分别设置有四个外引脚，其中一侧的四个外引脚分别和两个基岛的对应位置的对应侧相连通，另一侧的四个外引脚分别和两个基岛的对应位置的对应侧相互隔断；
所述芯片可通过绝缘胶装于所述基岛；
所述芯片可通过导电胶装于所述基岛；
两块所述芯片之间通过内引线键合连接。
采用本发明后，标准的SOP-8L封装引线框架的中心位置的基岛被分隔成两个基岛，基岛上可设置两块芯片，芯片通过内引线分别连接外引脚，之后完成对芯片的封装，其使得一个器件内能够同时封装两个相关联芯片，且无需外部连线，使得性能稳定，且使得产品芯片的封装小型化、微型化得以实现，一个器件同时也降低了成本。
附图说明
图1是本发明的结构示意图。
具体实施方式
见图1，其包括框架1、基岛、外引脚2，框架1的上下侧分别设置有四个外引脚2，框架1的中心位置设置有左右两个基岛，分别为左基岛3、右基岛4，左基岛3的上部连通上侧的左侧的两个外引脚2、并和下侧的左侧的两个外引脚2相互隔断，右基岛4的上部连通上侧的右侧的两个外引脚2、并和下侧的右侧的两个外引脚2相互隔断，左芯片5通过绝缘胶装于左基岛3上，右芯片6通过导电胶装于右基岛4上，左芯片5、右芯片6间通过内引线7键合连接，左芯片5通过内引线7连接至对应的外引脚3，右芯片6由于采用导电胶装于右基岛4，故其直接和右基岛4相连通的外引脚3相连接，右芯片6通过内引线7连接至其余外引脚3。

Claims (5)

1.一种SOP-8L封装引线框架，其包括框架、基岛、外引脚，所述框架的中心位置设置有基岛，所述框架的其中一对侧分别设置有外引脚，其特征在于：所述框架的中心位置设置有两个基岛，装于所述基岛上的芯片通过内引线分别连接对应的外引脚。
2.根据权利要求1所述的一种SOP-8L封装引线框架，其特征在于：所述框架的其中一对侧分别设置有四个外引脚，其中一侧的四个外引脚分别和两个基岛的对应位置的对应侧相连通，另一侧的四个外引脚分别和两个基岛的对应位置的对应侧相互隔断。
3.根据权利要求2所述的一种SOP-8L封装引线框架，其特征在于：所述芯片可通过绝缘胶装于所述基岛。
4.根据权利要求2所述的一种SOP-8L封装引线框架，其特征在于：所述芯片可通过导电胶装于所述基岛。
5.根据权利要求1至4中任一权利要求所述的一种SOP-8L封装引线框架，其特征在于：两块所述芯片之间通过内引线键合连接。
CN2013102914455A 2013-07-12 2013-07-12 一种sop-8l封装引线框架 Pending CN103337489A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2013102914455A CN103337489A (zh) 2013-07-12 2013-07-12 一种sop-8l封装引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2013102914455A CN103337489A (zh) 2013-07-12 2013-07-12 一种sop-8l封装引线框架

Publications (1)

Publication Number Publication Date
CN103337489A true CN103337489A (zh) 2013-10-02

Family

ID=49245625

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2013102914455A Pending CN103337489A (zh) 2013-07-12 2013-07-12 一种sop-8l封装引线框架

Country Status (1)

Country Link
CN (1) CN103337489A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811457A (zh) * 2014-02-18 2014-05-21 江阴苏阳电子股份有限公司 多芯片sop封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US201216A (en) * 1878-03-12 Improvement in breech-loading fire-arms
CN201340853Y (zh) * 2008-12-27 2009-11-04 无锡华润安盛科技有限公司 一种sop/msop/tssop的引线框结构
CN102364680A (zh) * 2011-10-28 2012-02-29 无锡红光微电子有限公司 Dip封装引线框架
US20120164794A1 (en) * 2010-12-28 2012-06-28 Yan Xun Xue Method of making a copper wire bond package
CN202712172U (zh) * 2012-07-25 2013-01-30 深圳市气派科技有限公司 一种多芯片双基岛的sop封装结构
CN203415571U (zh) * 2013-07-12 2014-01-29 无锡红光微电子有限公司 一种sop-8l封装引线框架

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US201216A (en) * 1878-03-12 Improvement in breech-loading fire-arms
CN201340853Y (zh) * 2008-12-27 2009-11-04 无锡华润安盛科技有限公司 一种sop/msop/tssop的引线框结构
US20120164794A1 (en) * 2010-12-28 2012-06-28 Yan Xun Xue Method of making a copper wire bond package
CN102364680A (zh) * 2011-10-28 2012-02-29 无锡红光微电子有限公司 Dip封装引线框架
CN202712172U (zh) * 2012-07-25 2013-01-30 深圳市气派科技有限公司 一种多芯片双基岛的sop封装结构
CN203415571U (zh) * 2013-07-12 2014-01-29 无锡红光微电子有限公司 一种sop-8l封装引线框架

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811457A (zh) * 2014-02-18 2014-05-21 江阴苏阳电子股份有限公司 多芯片sop封装结构

Similar Documents

Publication Publication Date Title
CN101506975B (zh) 堆叠管芯封装
WO2011090574A3 (en) Semiconductor package and method
CN102646663B (zh) 半导体封装件
CN104241220A (zh) 一种超小尺寸无塑封装
CN103325755A (zh) 半导体封装结构
CN103199075A (zh) 具堆叠芯片的晶圆级半导体封装构造及其制造方法
KR20150045095A (ko) 인터포저 제조방법 및 이를 이용한 적층형 패키지와 그 제조방법
US9299626B2 (en) Die package structure
US20150008593A1 (en) Stacked semiconductor device and method for manufacturing the same
CN103413801A (zh) 一种dfn封装引线框架
CN203415571U (zh) 一种sop-8l封装引线框架
CN100466246C (zh) 用于封装的柔性基板
CN103337489A (zh) 一种sop-8l封装引线框架
CN203573973U (zh) 一种dfn封装引线框架
US9362212B1 (en) Integrated circuit package having side and bottom contact pads
US20140146497A1 (en) Helix substrate and three-dimensional package with same
CN102364680A (zh) Dip封装引线框架
CN203573978U (zh) 芯片封装结构
CN103354226B (zh) 堆叠封装器件
CN104909330A (zh) 微机电模块以及其制造方法
CN103400811A (zh) 一种基于框架采用特殊点胶技术的扁平封装件及其制作工艺
CN202259274U (zh) 一种dip封装引线框架
CN204271072U (zh) 引线框架封装结构
CN203481210U (zh) 一种基于框架采用点胶技术的扁平封装件
KR101363993B1 (ko) 적층 반도체 패키

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20131002