CN210723009U - 带有转接板的qfn结构 - Google Patents

带有转接板的qfn结构 Download PDF

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CN210723009U
CN210723009U CN201922115701.0U CN201922115701U CN210723009U CN 210723009 U CN210723009 U CN 210723009U CN 201922115701 U CN201922115701 U CN 201922115701U CN 210723009 U CN210723009 U CN 210723009U
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wafer
qfn
adapter plate
pins
welding
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金若虚
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Yuancheng Technology (Suzhou) Co.,Ltd.
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Powertech Technology Suzhou Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型公开了一种带有转接板的QFN结构，其涉及半导体封装技术领域。旨在解决现有晶片焊垫位置与金属支架引脚位置不匹配则无法采用QFN封装形式的问题。其技术方案要点包括金属支架和晶片，所述金属支架上设置有若干引脚，所述晶片上设置有若干焊垫，所述引脚与焊垫之间连接有焊线，所述晶片上设置有转接板，所述引脚与焊垫之间可以通过所述转接板与焊线配合进行连接。本实用新型能够解决晶片焊垫位置与QFN对应信号引脚位置不匹配的问题，从而能够采用QFN封装形式，降低生产成本。

Description

带有转接板的QFN结构
技术领域
本实用新型涉及半导体封装技术领域，更具体地说，它涉及一种带有转接板的QFN结构。
背景技术
QFN金属支架引脚位置固定，需要通过金属焊线使晶片焊垫与QFN金属支架对应信号的引脚实现互联。所以如果晶片焊垫位置与QFN金属支架引脚位置不匹配，甚至交叉，就不能采用QFN的封装形式，而只能改为使用价格更高的封装基板，采用LGA/BGA的封装形式，使封装成本增加。
实用新型内容
针对现有技术存在的不足，本实用新型的目的在于提供一种带有转接板的QFN结构，其能够解决晶片焊垫位置与QFN对应信号引脚位置不匹配的问题，从而能够采用QFN封装形式。
为实现上述目的，本实用新型提供了如下技术方案：
一种带有转接板的QFN结构，包括金属支架和晶片，所述金属支架上设置有若干引脚，所述晶片上设置有若干焊垫，所述引脚与焊垫之间连接有焊线，所述晶片上设置有转接板，所述引脚与焊垫之间可以通过所述转接板与焊线配合进行连接。
进一步地，所述转接板上设置有布线电路。
进一步地，所述转接板与所述晶片为粘接。
综上所述，本实用新型具有以下有益效果：
采用了转接板能够解决晶片焊垫位置与QFN对应信号引脚位置不匹配的问题，使得不能生产的原始设计得以采用QFN封装形式实现量产。
附图说明
图1为实施例中带有转接板的QFN结构的示意图一；
图2为实施例中带有转接板的QFN结构的示意图二；
图3为实施例中没有转接板的QFN结构的示意图。
图中：1、金属支架,11、引脚；2、晶片；21、焊垫；3、转接板；4、焊线。
具体实施方式
以下结合附图对本实用新型作进一步详细说明。
本具体实施例仅仅是对本实用新型的解释，其并不是对本实用新型的限制，本领域技术人员在阅读完本说明书后可以根据需要对本实施例做出没有创造性贡献的修改，但只要在本实用新型的权利要求范围内都受到专利法的保护。
实施例：
一种带有转接板的QFN结构，参照图1和图2，其包括金属支架1和晶片2，金属支架1上设置有若干引脚11，晶片2上设置有若干焊垫21，引脚11与焊垫21之间连接有焊线4；本实施例中晶片2上粘贴有转接板3，引脚11与焊垫21之间可以通过转接板3与焊线4配合进行连接，即焊垫21通过焊线4与转接板3连接，再由转接板3通过焊线4连接到对应信号的引脚11上。
参照图2和图3，转接板3上设置有布线电路，布线电路可以根据需求设计，实现自定义布线，即转接板3可以为印刷电路板；图3原始设计焊线图无法实现量产，图2采用转接板3后的焊线图中，部分焊线4的长度和角度都有改善，使得不能生产的原始设计得以采用QFN封装形式实现量产。

Claims (3)

1.一种带有转接板的QFN结构，包括金属支架和晶片，所述金属支架上设置有若干引脚，所述晶片上设置有若干焊垫，所述引脚与焊垫之间连接有焊线，其特征在于：所述晶片上设置有转接板，所述引脚与焊垫之间可以通过所述转接板与焊线配合进行连接。
2.根据权利要求1所述的带有转接板的QFN结构，其特征在于：所述转接板上设置有布线电路。
3.根据权利要求1或2所述的带有转接板的QFN结构，其特征在于：所述转接板与所述晶片为粘接。
CN201922115701.0U 2019-11-29 2019-11-29 带有转接板的qfn结构 Active CN210723009U (zh)

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Address after: 215000 33 Xinghai street, Suzhou Industrial Park, Suzhou City, Jiangsu Province

Patentee after: Yuancheng Technology (Suzhou) Co.,Ltd.

Address before: 215000 33 Xinghai street, Suzhou Industrial Park, Suzhou City, Jiangsu Province

Patentee before: Powertech Technology (Suzhou) Co.,Ltd.