CN210692525U - 一种sot双芯片引线框架结构 - Google Patents
一种sot双芯片引线框架结构 Download PDFInfo
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- CN210692525U CN210692525U CN201922118853.6U CN201922118853U CN210692525U CN 210692525 U CN210692525 U CN 210692525U CN 201922118853 U CN201922118853 U CN 201922118853U CN 210692525 U CN210692525 U CN 210692525U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Abstract
一种SOT双芯片引线框架结构，包括内引脚、外引脚以及两个用于安装芯片的基岛，所述基岛以及所述内引脚均位于一四边形框架结构内，框架结构内的一侧的横边排列有3个内引脚，框架结构内的另一侧横边的中部设置有1个内引脚，框架结构外的一侧的横边上依次设置有3个外引脚，框架结构外的另一侧的横边上依次设置有3个外引脚，两个基岛分别位于框架结构内竖向中线的左右两侧，每个内引脚分别连接外引脚的内端，基岛的另一侧分别连接一个外引脚的内端。本实用新型体积小，散热快。
Description
技术领域
本实用新型属于电子产品技术领域，具体涉及到一种SOT双芯片引线框架结构。
背景技术
芯片封装，是一种将集成电路用绝缘的塑料或陶瓷材料打包的技术，不仅起到安放、固定、密封、保护芯片和增强导热性能的作用，而且还是沟通芯片内部世界与外部电路的桥梁。
小外形晶体管封装(SOT,Small Outline Transistor)是目前常用的一种小型贴片式封装。MOS管是目前十分常见的一种分立器件，相对IC而言，由于其独特的开关特性具有不可替代的优势，广泛应用在消费类、便携式电子产品中。就目前而言，双管MOS芯片的应用范围比多管芯的更广更灵活一些。目前，双管芯片封装具有体积大、散热差的缺点。
实用新型内容
本实用新型的目的在于克服上述现有技术中双管MOS芯片封装结构体积大以及散热差的不足，提供了一种SOT双芯片引线框架结构。
本实用新型是这样实现的：一种SOT双芯片引线框架结构，包括内引脚、外引脚以及两个用于安装芯片的基岛，所述基岛以及所述内引脚均位于一四边形框架结构内，框架结构内的一侧的横边排列有3个内引脚，框架结构内的另一侧横边的中部设置有1个内引脚，框架结构外的一侧的横边上依次设置有3个外引脚，框架结构外的另一侧的横边上依次设置有3个外引脚，两个基岛分别位于框架结构内竖向中线的左右两侧，每个内引脚分别连接外引脚的内端，基岛的另一侧分别连接一个外引脚的内端。
优选地：两基岛在靠近框架结构竖向中线的另一侧分别设置有用以容纳内引脚的凹部。
有益效果：本实用新型体积小，散热快。
附图说明
图1是本实用新型实施例提供的SOT双芯片引线框架结构的结构示意图。
附图标记名称如下：11、第一基岛；12、第二基岛；21、第一芯片；22、第二芯片；30、焊线；40、外引脚；50、内引脚；61、第一凹部；62、第二凹部。
具体实施方式
一种SOT双芯片引线框架结构，包括内引脚50、外引脚40以及两个用于安装芯片（21、22）的基岛（11、12）。其中，第一芯片21安装在第一基岛11上，第二芯片22安装在第二基岛12上，所述第一基岛11、第二基岛12以及所述内引脚50均位于一四边形的框架结构内，第一基岛11、第二基岛12分别位于框架结构竖向中线的左右两侧。外引脚40的数量为6个，框架结构外的一侧的横边上依次设置有3个外引脚40，框架结构外的另一侧的横边上依次设置有3个外引脚40。所述内引脚50的数量为4个，框架结构内的一侧的横边依次排列有3个内引脚，框架结构内的另一侧横边的中部设置有1个内引脚。第一芯片21、第二芯片22分别通过焊线30与对应的内引脚40相连。每个所述内引脚50分别连接一个外引脚40的内端，第一基岛11、第二基岛12分别与框架结构外的另一侧横边上外引脚40的内端连接。第一基岛11在靠近框架结构竖向中线的另一侧设置有用以容纳内引脚50的第一凹部61，第二基岛12在靠近框架结构竖向中线的另一侧设置有用以容纳内引脚50的第二凹部62。框架结构另一侧中部的内引脚50位于第一凹部61、第二凹部62之间，通过将该内引脚50设置在第一基岛11、第二基岛12之间的凹部，使得框架结构内的基岛及内引脚结构更紧凑，节约了空间，减小了框架结构的体积，同时，在不改变框架结构内的面积的情况下，可以增加框架结构内基岛的面积，提高了基岛的传导面积，提高了散热效率。
本实用新型提供的一种SOT双芯片引线框架结构，相对于现有技术，其具有6个有效的外引脚，两个基岛，可适用于封装两颗分别需要6个引出端子的芯片，尤其是两颗MOS管芯的产品(双N管、双P管或N+P复合管)。
上述中，可以理解的是，除非另外定义，本实用新型使用的技术术语或者科学术语应当为本实用新型所属领域内具有一般技能的人士所理解的通常意义。本实用新型中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“一侧”、“另一侧”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
Claims (2)
1.一种SOT双芯片引线框架结构，包括内引脚、外引脚以及两个用于安装芯片的基岛，其特征在于：所述基岛以及所述内引脚均位于一四边形框架结构内，框架结构内的一侧的横边排列有3个内引脚，框架结构内的另一侧横边的中部设置有1个内引脚，框架结构外的一侧的横边上依次设置有3个外引脚，框架结构外的另一侧的横边上依次设置有3个外引脚，两个基岛分别位于框架结构内竖向中线的左右两侧，每个内引脚分别连接外引脚的内端，基岛的另一侧分别连接一个外引脚的内端。
2.如权利要求1所述的SOT双芯片引线框架结构，其特征在于：两基岛在靠近框架结构竖向中线的另一侧分别设置有用以容纳内引脚的凹部。
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