CN201946589U - 一种改进的引线框架 - Google Patents

一种改进的引线框架 Download PDF

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CN201946589U
CN201946589U CN2010206744629U CN201020674462U CN201946589U CN 201946589 U CN201946589 U CN 201946589U CN 2010206744629 U CN2010206744629 U CN 2010206744629U CN 201020674462 U CN201020674462 U CN 201020674462U CN 201946589 U CN201946589 U CN 201946589U
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lead frame
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管军华
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Core (chengdu) Integrated Circuit Package Testing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

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Abstract

本实用新型公开了一种改进的引线框架，涉及半导体封装的引线框架，旨在提供一种将部分管脚与焊垫片连接的引线框架。本实用新型能够有效节省引线框架中用于放置集成电路芯片与增加芯片引脚的空间，避免了不完全引脚的出现。本实用新型采用了以下技术方案：将引线框架中的某些管脚（2）与焊垫片（1）连接。本实用新型可用于各种封装的引线框架。

Description

一种改进的引线框架
技术领域
本实用新型涉及半导体封装的引线框架，特别是一种连接部分管脚与焊垫片的引线框架。
背景技术
引线框架作为集成电路的芯片载体，是一种借助于打线（通常是金线、铝线或铜线）将芯片内部电路导出封装体，同时承载部分散热功能。引线框架主要包括焊垫片、管脚、连接筋三部分，焊垫片用以承载集成电路芯片，管脚用于连接芯片和印刷电路板，连接筋是为了将焊垫片固定在外围承载体上。引线框架不仅具有连接半导体封装内部与外部的功能，还具支承半导体芯片的功能。
在现有的集成电路或分立器件的设计中，一方面一些集成电路设计需要将焊垫片和某个管脚设计成相同的输出信号，而现有引线框架的管脚与焊垫片是彼此分离的，因此需要一根额外的打线将接地管脚与焊垫片连接起来。而通过打线将管脚与焊垫片连接，则需要在焊垫片上预留一定的空间，这样实际就会要求芯片的尺寸变小一些，当芯片尺寸过大时，现有的引线框架设计特点不能提供足够的空间实现此接地要求，见图1和图2；另一方面，例如图2中所示的QFN4×4封装体，基于目前表面粘接技术，如果管脚的间距是0.5mm，做多的管脚数量是24个；如果管脚的间距是0.4mm，最多可以设计的管脚数量是32个。现有的引线框架在焊垫片的4个角上设计有连接筋，由于空间限制，4个角落的管脚都是不完全的，这样会对集成电路的测试和上板带来一些问题。比如测试接触面积过小，造成过度报废；上板时有虚焊，或无法焊接等问题；因此需要在有限的封装体尺寸和最小的管脚间距和尺寸要求基础上去掉用于固定焊垫片的连接筋从而多设计一些管脚，现有的引线框架不能实现此设计要求。
实用新型内容
本实用新型的发明目的在于：在保证封装外形不变的前提条件下，针对上述存在的缺陷，提供一种连接管脚的引线框架。
本实用新型采用的技术方案是这样的：包括装载半导体元件的焊垫片1、管脚2、连接筋5，所述连接筋5与焊垫片1连接，其特征在于，焊垫片1与N只管脚2连接，所述N大于等于1且小于引线框架中管脚2的总数。
优选地，焊垫片1与管脚2的连接方式为焊接，或者管脚2由焊垫片1延伸出来的部分构成。
一种改进的引线框架，包括装载半导体元件的焊垫片、管脚，其特征在于，焊垫片1与N只管脚2连接；所述N大于等于1且小于引线框架中管脚2的总数。
优选地，所述引线框架的封装为四方形，4条边上各有一只管脚2与焊垫片1连接。
优选地，所述引线框架的封装为四方形，其中3条边上各有一只管脚2与焊垫片1连接。
优选地，所述引线框架的封装为四方形，其中2条相对的边上各有一只管脚2与焊垫片1连接。
优选地，焊垫片1与管脚2连接的方式为焊接或者管脚2由焊垫片1延伸出来的部分构成。
综上所述，本实用新型的有益效果是：
1、在引线框架设计的时候，将焊垫片和部分接地管脚短接起来。既可以给芯片预留较多的空间，又可以减少打线的数量。对于某些需要更多功能，而 不能缩小尺寸的芯片需要来说，是一个很好的解决方法。
2、用与焊垫片连接的管脚代替连接筋实现固定焊垫片的作用，为其余管脚预留了较多的空间，避免了不完全管脚的出现。
3、本实用新型在实现上述两条有益效果时，同时保证了其封装外形不变，以满足各类封装的统一标准。
附图说明
图1是现有技术引线框架内部结构图。
图2是现有技术引线框架内部打线图。
图3是现有技术引线框架封装后的外形图。
图4是现有技术中四方形封装引线框架内部结构图。
图5是现有技术中四方形封装引线框架封装后的外形图。
图6是本实用新型第一实施例引线框架内部结构图。
图7是本实用新型第一实施例引线框架内部打线图。
图8是本实用新型第一实施例引线框架封装后的外形图。
图9是本实用性第二实施例引线框架内部结构图。
图10是本实用新型第二实施例引线框架封装后的外形图。
图中标记：焊垫片1  管脚2  集成电路芯片3  打线4  连接筋5  不完全管脚6  与焊垫片焊接后的管脚7。
具体实施方式
下面结合附图与实施例，对本实用新型作详细的说明。
为了使本实用新型的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本实用新型进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本实用新型，并不用于限定本实用新型。
图6所示的是本实用新型第一种事实例，包括焊垫片、管脚与连接筋，焊垫片与其中一个管脚连接，所述连接的方式可以仅为物理上的连接而不需要导电连接，当连接方式为非导电的物理连接时，仅起到连接筋的作用；当需要连接的管脚为接地管脚是便可以采用导电连接，导电连接的方式又可以为焊接，也可以需要连接的管脚是焊垫片延伸出来的一部分，当连接方式为导电的物理连接时，此连接在起到连接筋作用的同时还起短接焊垫片与接地管脚的作用。图7为图6所示引线框架的内部打线连接图，其中管脚与焊垫片的连接方式为导电连接，芯片3固定在焊垫片2上，芯片3上需要与外部连接的端子通过打线4分别接到不同的管脚，其中芯片3上需要接地的端子均被连接到与焊垫片1短接的管脚2上，在设计中焊垫片是接地的，因此芯片3上需要接地的端子通过与焊垫片1相连的管脚2实现了接地。图8为本实施例封装后的外形图，与图3所示的现有引线框架封装后的外形没有区别。
图9所示的是QFN4x4封装的引线框架内部结构，在焊垫片1的4条边上各有个脚上一个管脚2与焊垫片1连接。作为本实施例的一种变形，根据实际需要也可以只在焊垫片1的3条边上各有一个管脚2与焊垫片1连接；作为本事实例的另一种变形，焊垫片1上相对的2条边上各有一个管脚2与焊垫片1连接。本事实例中焊垫片1与管脚2的连接方式也可以有非导电的物理连接和到点连接两种。本事实例中，由被连接的管脚能够起到连接筋的作用，因此去掉了引线框架中的连接筋，预留了更多的空间，避免了不完全管脚的出现。图10为本实施例封装后的外形图，与现有的此类引线框架封装后的外形没有区别。
以上所述仅为本实用新型的较佳实施例而已，并不用以限制本实用新型，凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本实用新型的保护范围之内。

Claims (7)

1.一种改进的引线框架，包括装载半导体元件的焊垫片（1）、管脚（2）、连接筋（5），所述连接筋（5）与焊垫片（1）连接，其特征在于，焊垫片（1）与N只管脚（2）连接；所述N大于等于1且小于引线框架中管脚（2）的总数。
2.根据权利要求1所述的一种改进的引线框架,其特征在于，焊垫片（1）与管脚（2）的连接方式为焊接，或者管脚（2）由焊垫片（1）延伸出来的部分构成。
3.一种改进的引线框架，包括装载半导体元件的焊垫片、管脚，其特征在于，焊垫片（1）与N只管脚（2）连接；所述N大于等于1且小于引线框架中管脚（2）的总数。
4.根据权利要求3所述的一种改进的引线框架，其特征在于，所述引线框架的封装为四方形，4条边上各有一只管脚（2）与焊垫片（1）连接。
5.根据权利要求3所述的一种改进的引线框架，其特征在于，所述引线框架的封装为四方形，其中3条边上各有一只管脚（2）与焊垫片（1）连接。
6.根据权利要求3所述的一种改进的引线框架，其特征在于，所述引线框架的封装为四方形，其中2条相对的边上各有一只管脚（2）与焊垫片（1）连接。
7.根据权利要求3或4或5或6所述的一种改进的引线框架，其特征在于，焊垫片（1）与管脚（2）连接的方式为焊接或者管脚（2）由焊垫片（1）延伸出来的部分构成。
CN2010206744629U 2010-12-22 2010-12-22 一种改进的引线框架 Expired - Lifetime CN201946589U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117263A (zh) * 2013-01-31 2013-05-22 建荣集成电路科技(珠海)有限公司 一种集成电路封装
CN109192715A (zh) * 2018-09-20 2019-01-11 江苏长电科技股份有限公司 引线框结构、封装结构及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117263A (zh) * 2013-01-31 2013-05-22 建荣集成电路科技(珠海)有限公司 一种集成电路封装
CN109192715A (zh) * 2018-09-20 2019-01-11 江苏长电科技股份有限公司 引线框结构、封装结构及其制造方法
CN109192715B (zh) * 2018-09-20 2024-03-22 江苏长电科技股份有限公司 引线框结构、封装结构及其制造方法

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