CN215600361U - 集成电路封装件和电子设备 - Google Patents

集成电路封装件和电子设备 Download PDF

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CN215600361U
CN215600361U CN202120282004.9U CN202120282004U CN215600361U CN 215600361 U CN215600361 U CN 215600361U CN 202120282004 U CN202120282004 U CN 202120282004U CN 215600361 U CN215600361 U CN 215600361U
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integrated circuit
lines
electronic device
solder balls
distance
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A·斯库德里
N·马里内利
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STMicroelectronics SRL
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STMicroelectronics SRL
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Abstract

实施例公开了集成电路封装件及电子设备。一种集成电路封装件，包括：管芯，包括半导体材料和集成电子元件；连接区域，覆盖在实用新型管芯上；以及多个焊球，被固定到实用新型连接区域并且被电耦合到实用新型电子元件，实用新型焊球被布置成阵列并且沿着与一个方向平行的多条线被对齐，其中实用新型多条线包括空线，沿着实用新型空线不存在焊球。本公开的实施例提供了布局简单、成本低、以及具有改进的信号质量的集成电路封装件及电子设备。

Description

集成电路封装件和电子设备
技术领域
本公开涉及一种集成电路和一种电子设备，该电子设备包括通过同步信号电耦合的多个集成电路。
背景技术
特别地，这种类型的电子设备用于射频应用中，例如用于机动车辆(通常，在76GHz至81GHz的频率范围内)的雷达中，其中存在多个发射信道和/或接收信道，和/或用于成像应用中，例如用于医疗用途。
在这些类型的多信道应用中，目前MMIC(单片微波集成电路)由于其均匀的电气特性(通常，它们与50Ω的阻抗匹配)，被越来越多地使用，这使得它们易于使用，因为它们可以很容易地级联连接，而不需要任何外部阻抗匹配网络。
以这种方式，可以制造由多个级联连接的MMIC形成的设备，其中每个MMIC被配置为管理少量的发射信道/接收信道。例如，MMIC可以被连接在一起，使得第一MMIC(称为主MMIC)生成同步信号并将这些信号提供给所有其他MMIC(称为从属MMIC)。特别地，主MMIC根据应用以或多或少的高频率(例如，在20、40或80GHz下)生成同步信号LO。通过这种布置，所有MMIC接收来自主MMIC的同步信号LO，并且能够使用发射天线和接收天线连接，以同步方式发射和接收射频信号。
例如，以这种方式，高端雷达设备能够使用三个MMIC(一个主MMIC和两个从属MMIC)来管理12个接收信道(下文称为“RX信道”)和9个发射信道(下文称为“TX信道”)，每个MMIC能够管理四个RX信道和三个TX信道。更一般地说，这种类型的雷达设备能够使用每个能够管理X/M个RX信道和Y/M个TX信道的M个MMIC来管理X个RX信道和Y个TX信道。
通常，此外，用于发射/接收射频信号的基于MMIC的设备包括承载MMIC和天线的印刷电路板(PCB)，并且可以具有图1中所示和下文所述的类型的布局。
例如，图1示出了设备1，设备1包括印刷电路板(PCB 2)，印刷电路板(PCB 2)承载一个主MMIC 3和三个从属MMIC 4至6(即使MMIC的数目可以更大或更小)。在图1的俯视图中，MMIC 3至6并排设置在接收天线结构(图1中顶部的RX天线10)和发射天线结构(图1中底部的TX天线11)之间。
高频MMIC 3至6通常被固定到PCB 2并且通过焊球连接电连接在一起，如下文更详细地描述。PCB 2具有表面电连接13，通常形成为PCB 2表面上的导电迹线，用于将MMIC 3至6电连接到RX天线10和TX天线11；掩埋的电连接14，由导电迹线形成，通常在PCB 2的内层中延伸；以及连接过孔，用于连接PCB 2的不同层(level)和表面，用于以已知的方式在MMIC 3至6之间交换信号和电量，并且仅在图1中示意性地示出。
在射频应用中，由于高工作频率(通常高于40GHz)，焊球连接目前通过FC-BGA(倒装芯片球栅阵列)技术或eWLB(嵌入式晶片级BGA)技术实现。
众所周知，这两种技术都使用固定在每个MMIC 3至6的一侧(例如，在背侧)上的球栅阵列15来耦合到PCB 2，如图2中所例示的，其中焊球由15标示，通用MMIC由16标示。
在FC-BGA技术的情况下(参见图3，其是通过通用MMIC 16的横截面)，焊球15被固定到由容纳介电材料9的两个板8形成的连接基底7的一侧。介电材料9嵌入金属连接线18，金属连接线18将焊球15与固定到焊球15相对侧的连接基底7上的凸块17电连接。此外，凸块17被固定到容纳电子元件(由22整体标示)的管芯21上，并且使得信号和可能的其他电量(例如，供应量，在下文被包括在术语“信号”中)能够在每个MMIC 3至6的电子元件22和连接基底7之间通过。介电填充和匹配层(所谓的底部填充层19)在管芯21与连接基底7之间延伸并覆盖凸块17。盖12通过粘结层23键合到连接基底7并且包围管芯21、凸块17和底部填充层19，以与连接基底7形成一种封装件。
在eWLB技术的情况下(参见图4，示出了通过通用MMIC 16的一部分的横截面)，每个焊球15通常被固定到相应的导电区域25。导电区域25(仅示出其中一个)通常由介电层26内的铜制成，并且形成一个或多个再分配层(在图4中，单个再分配层RDL 24)。介电层26在覆盖管芯28的钝化层27上延伸，除了接触焊盘30处的开口之外，该接触焊盘30形成在管芯28的表面上并且被电连接到集成在管芯28中的电子元件(由31整体标示)。这里，管芯28被外围区域29包围。外围区域29通常通过压缩成型来制造并加宽管芯28的面积，使得介电层26(也在外围区域29上延伸)可具有比管芯28更大的面积，使得焊球15能够以例如500μm的间距被布置在比管芯28更大的面积上。
eWLB技术允许获得互连的最小长度和高达高频率(波长在毫米范围内)的非常好的电气性能，不需要在底部填充底部填充材料，使得具有多个输入/输出连接成为可能，并且具有低成本。
在MMIC 3至6之间交换的信号中，特别重要的是同步信号LO，因为它使得维持MMIC3至6之间的相位相干性和放大平衡成为可能。
目前，同步信号LO(具有两个不同的输入以使得能够在PCB 2中对称路由)使用PCB2的内部附加层通过掩埋的连接14而被路由，因为这些同步连接不能在PCB 2的顶层上形成，以避免与RX天线10和TX天线11交叉表面电连接13(图1)。
然而，这导致掩埋的连接14的复杂性以及形成PCB 2的内部附加层的高成本增加。此外，各个层之间的转换增加，这导致信号振幅的不需要的下降。
实用新型内容
鉴于上述MIMC设备所面临的布局、成本、信号质量等方面存在的问题，本公开提供了一种集成电路和电子设备，该集成电路和电子设备使用电流连接技术(例如，基于焊球的电流连接技术)克服了现有技术的缺点。
根据本公开，提供了一种集成电路封装件和电子设备。
在至少一个实施例中，提供了一种包括管芯的集成电路封装件，该管芯包括半导体材料和集成电子元件。连接区域覆盖在管芯上。多个焊球被固定到连接区域并且被电耦合到电子元件，并且焊球被布置成阵列并沿着与一个方向平行的多条线对齐。多条线包括空线，沿着空线不存在焊球。
在一些实施例中，第一线以相互均匀的第一距离被布置，并且第一相邻线属于多条线并且与空线直接相邻，第一相邻线以相互的第二距离被布置，第二距离大于第一距离。
在一些实施例中，第二距离是第一距离的两倍。
在一些实施例中，集成电路封装件是单片微波集成电路封装件。
在至少一个实施例中，提供了一种电子设备，该电子设备包括具有面的支撑件和多个集成电路。每个集成电路都具有集成电子元件。每个集成电路包括多个焊球，并且多个焊球被电耦合到相应的集成电路的电子元件，并且焊球被固定在支撑件的面与相应的集成电路之间。天线结构被布置在支撑件的面上。电连接路径被布置在支撑件的面上并且将天线结构电耦合到每个集成电路的多个焊球的第一焊球。每个集成电路的多个焊球被布置成阵列并沿着与一个方向平行的多条线对齐，并且多条线包括不存在焊球的空线。导电同步路径在支撑件的面上延伸并且被电耦合到每个集成电路的至少第一焊球。导电同步路径具有沿着多个集成电路中的至少一个集成电路的空线延伸的至少第一部分。
在一些实施例中，导电同步路径被多个集成电路中的至少一个集成电路的焊球横向包围。
在一些实施例中，第一线以相互均匀的第一距离被布置，并且相邻线属于多条线并且与空线直接相邻，相邻线以相互的第二距离被布置，第二距离大于第一距离。
在一些实施例中，第二距离是第一距离的长度的两倍。
在一些实施例中，至少一个集成电路形成主集成电路，并且包括输出端子，输出端子被耦合到第二焊球并且被配置为生成同步信号；多个集成电路包括第一从属集成电路和第二从属集成电路，第一从属集成电路和第二从属集成电路被布置在主集成电路的不同侧上；并且导电同步路径具有在支撑件的面上延伸的连接部分，连接部分从第一部分分支并且被耦合到主集成电路以及第一从属集成电路和第二从属集成电路这三者的第一焊球。
在一些实施例中，连接部分包括：第一连接部分，在主集成电路与第一从属集成电路之间延伸；第二连接部分，在主集成电路与第二从属集成电路之间延伸；第三连接部分，在第一部分与主集成电路的相应的第一焊球之间延伸；以及第四连接部分，在第二部分与主集成电路的第二焊球之间延伸，第三连接部分和第四连接部分在主集成电路的相对侧上延伸。
在一些实施例中，焊球形成倒装芯片球栅阵列耦合或嵌入式晶片级BGA耦合。
在一些实施例中，集成电路是单片微波集成电路。
在一些实施例中，电子设备是微波雷达设备。
在至少一个实施例中，提供了一种电子设备，该电子设备包括具有表面的印刷电路板(PCB)和被物理地连接到PCB表面的半导体设备封装件。半导体设备封装件包括具有集成电子元件的半导体管芯、在半导体管芯上的连接区域、以及被连接到连接区域并且被电耦合到电子元件的多个焊球。焊球被布置成阵列并沿着与一个方向平行的多条线对齐。多条线包括沿着不存在焊球的空线。
在一些实施例中，第一线以相互均匀的第一距离被布置，并且第一相邻线属于多条线并且与空线直接相邻，第一相邻线以相互的第二距离被布置，第二距离大于第一距离。
在一些实施例中，第二距离是第一距离的两倍。
在一些实施例中，半导体设备封装件是单片微波集成电路封装件。
在一些实施例中，多个焊球形成倒装芯片球栅阵列耦合或嵌入式晶片级BGA耦合。
在一些实施例中，电子设备是微波雷达设备。
在一些实施例中，电子设备进一步包括：天线，在PCB的表面上，并且被电耦合到半导体设备封装件。
本公开的实施例提供了布局简单、成本低、以及具有改进的信号质量的集成电路封装件及电子设备。
附图说明
为了更好地理解本公开，现在仅通过非限制性示例，参考附图来描述本公开的一些实施例，其中：
图1示出了具有多个用于已知类型的射频应用的集成电路的电子设备的布局；
图2是被配置为使用球栅阵列技术键合的集成电路的底部立体视图；
图3是被配置为使用FC-BGA技术键合的图2的集成电路的一部分的横截面；
图4是被配置为使用eWLB技术键合图2的集成电路的一部分的横截面；
图5示出了根据实施例的具有多个集成电路的电子设备的布局；
图6是图5的集成电路的底视图；
图6A示出了图6的集成电路的放大的细节；
图7是图5的集成电路的一部分的横截面；
图8示出了根据另一实施例的具有多个集成电路的电子设备的布局；
图9是图8的电子设备的集成电路的一部分沿着截面线IX-IX的横截面；
图10是图9的集成电路沿着与图9相同的截面线的不同实施例；
图11示出了根据不同实施例的具有多个集成电路的电子设备的布局；
图12是图11的电子设备的集成电路的一部分沿着截面线XII-XII的横截面；以及
图13是图12的集成电路沿着与图12相同的截面线的不同实施例的横截面。
具体实施方式
图5示出了包括印刷电路板PCB 52的电子设备50，印刷电路板PCB 52承载四个MMIC，例如一个主MMIC 53和三个从属MMIC 54至56(尽管从属MMIC的数目可能不同)。在图5的俯视图中，MMIC 53至56并排布置在接收天线结构(图5中顶部的RX天线60)和发射天线结构(图5中底部的TX天线61)之间。
参考图7，MMIC 53至56包括容纳电子元件(由58示意性地表示并整体标示)的半导体设备封装件57(在一些实施例中，其可被称为管芯57)。连接区域59在管芯57上延伸。在eWLB键合技术的情况下，如上文参考图4所述，连接区域由容纳金属连接线61的介电层形成。在FC-BGA键合技术的情况下，连接区域59由与图3的键合支撑件7类似的键合支撑件形成。在图7中不可见的是可能的钝化层，或者在eWLB键合技术的情况下是围绕管芯57的可能的外围区域，或者在FC-BGA键合技术的情况下是底部填充层和凸块，但是它们可能存在，分别如图4和图3中所示。
再次参考图5，MMIC 53至56通过表面电连接63被连接到RX天线60和TX天线61，表面电连接63以已知的方式形成为承载MMIC 53至56的PCB 52的表面上的导电迹线。此外，如下文所述，MMIC 53至56通过在PCB 52中形成的掩埋的连接以及通过下文详细描述的同步线64相互连接，同步线64以本身已知的方式通过电子元件74路由由主MMIC 53生成的同步信号LO，并提供给从属MMIC 54至56以用于它们的同步和振幅平衡。
在下文中，为了能够更好地理解，从属MMIC 54至56也被称为第一从属MMIC 54、第二从属MMIC 55和第三从属MMIC 56。在所示的实施例中(具体参见图5)，主MMIC 53被布置在第一从属MMIC 54(位于左侧)与第二从属MMIC 55(位于右侧)之间。因此，同步信号LO穿过主MMIC 53和第二从属MMIC 55。
MMIC 53至56(也参见图6和图7)通过使用焊球65的焊球技术固定并被电连接到PCB 52。焊球65可以使用FC-BGA技术或者使用上文所述且在图3和图4中所示的eWLB技术而被键合。应该注意的是，下文将使用术语“球”，即使在键合后，它们通常变形并且具有与球形不同的形状。
如图6中所示，焊球65被布置成行和列，在图6中分别用字母A至Y和数字1至18标识，但在第J行上不存在焊球65。
以这种方式，第J行限定了空行或缺行，即被布置在相邻行(图6中的行K和行H)上的焊球65彼此之间布置的距离大于其他相邻行之间的距离。特别地，参考图6A的放大的细节，如果p表示阵列中相邻行之间的间距(即，属于相互相邻的行的焊球65的中心点之间的距离)，则在空行处，距离d是间距p的两倍(d＝2p)。
如图6中的虚线所示，同步线64(在PCB 52上)在空行中、在距离d处布置的焊球65的两行之间延伸。
参考图7，PCB 52以已知方式包括介电材料的主体67，该主体67具有第一面67A和第二面67B，并且嵌入连接在一起的导电区域68，并且通过用于在MMIC 53至56之间电连接的金属过孔69嵌入到第一面67A。可能的过孔(未示出)还可以将导电区域68连接到PCB 52的第二面67B。此外，PCB 52的第一面67A承载表面电连接63(这里不可见)和同步线64。
特别地(也参见图5)，同步线64在这里由同步迹线66形成，同步迹线66包括直线部分66A和分支部分66B，分支部分66B从直线部分66A延伸到被布置在MMIC 53至56的端子处的相应的焊球65，MMIC 53至56的端子旨在接收/发射同步信号LO(在图5中，用LOin表示输入端，用LOout表示输出端)。例如，连接到被耦合到图5的主MMIC 53的输入端子LOin和输出端子LOout的焊球65A的分支部分66B在图6中用虚线表示。
实际上，在图5中所示的实施例中，同步线64的直线部分66A仅在主MMIC 53和第二从属MMIC 85的下方延伸，即使所有MMIC 53至56都具有空行，并且分支部分66B被连接到主MMIC 53的两个焊球65(图6中的焊球65A和65B)和MMIC 54至56的单个焊球65。
然而，直线部分66A不一定由穿过主MMIC 53和第二从属MMIC 85的单个段形成，而是可以由折线形成，仅其穿过单个MMIC 53和55的部分优选为线性的。
同步迹线66可以以与在PCB 52的第一面67A上形成的表面电连接63相同的方式被形成，例如，作为铜迹线，并且通常具有比焊球65低得多的厚度，即使这些焊球在焊接后轻微变形，如图7中所示。
图8至图10示出了实现用于路由同步信号LO的不同解决方案的电子设备70。这里，MMIC包括微带(具有被布置在下方的接地区域)或共面波导(具有与波导在同一平面中的接地区域)。微带或共面波导在管芯上方形成，并且实际上在每个MMIC的整个宽度上延伸以连接其相对侧。与端子LOin和LOout的连接通过导电迹线获得，所述导电迹线形成在PCB上并且通过焊球连接到微带或共面波导。图8和图9中所示的关于通过eWLB技术键合MMIC的该解决方案还可以用于如下所述的通过FC-BGA技术键合MMIC的情况。
在图8和图9中，MMIC(这里由83至86标示)具有耦合面81，如图4中所示形成，并且每个MMIC包括集成电子元件(由74整体标示)的管芯73、外围区域76和介电层72。如上文参考图4所述，示意性地表示的金属连接线75在介电层72中延伸并且与焊球95连接。此外，同样在这里，为了清楚起见，从属MMIC 84至86被称为第一从属MMIC、第二从属MMIC和第三从属MMIC。应该注意的是，在这里，尽管未示出，但是以本身已知的方式，每个管芯73源于切割加工的半导体晶片并且包括半导体基底(未示出)，该半导体基底由容纳金属连接线(也未示出)的一个或多个绝缘层(未示出)覆盖。
此外，如图5中所示，在图8中，MMIC 83至86并排布置在接收天线结构RX天线90与发射天线结构TX天线91之间，并且通过在PCB(由92标示)上形成的表面电连接93被耦合到RX天线90和TX天线91，包括以已知的方式，嵌入导电区域98的介电材料的主体97，导电区域98通过金属过孔99连接在一起并连接到第一面97A。
特别地，关于图8和9的实施例，每个MMIC 83至86都具有在主MMIC 83和从属MMIC84至86的介电层72中形成的导电条带71。
导电条带71在这里使用再分配层RDL而形成。
图10示出了图9的变体，其中MMIC 83至86使用FC-BGA技术键合。
这里，电子设备(由70’标示)具有在金属层中形成的导电条带71’，该导电条带71’与用于在连接基底89内形成金属连接线88的导电条带类似，该金属连接线88与图3的金属连接线18类似，该连接基底89与图3的连接基底7类似。在图10中，板8未示出，底部填充层、凸块和盖分别由77、79和80标示。
在图9和图10的两种情况下，导电条带71、71’大致在MMIC 83至86的整个宽度(从而在介电层72或连接基底89的宽度)上延伸，仅在距离其边缘较短的距离处结束。
应该注意的是，在这种情况下，术语MMIC 53至56的宽度指示MMIC 53至56的邻接方向上的尺寸。
如图8中所示，电子设备70、70’具有由MMIC 83至86中(与同步线96交叉)的一些MMIC的导电条带71、71’形成的同步线96和在PCB 92上形成的迹线部分94。导电条带71、71’和形成同步线96的迹线部分94通过焊球95连接在一起。
详细地说，同步线96在这里由主MMIC 83和第二从属MMIC 85的导电条带71、71’形成(被布置在图9和图10中主MMIC 83的右侧)。导电条带71、71’不电耦合到任何元件74，并且仅连接到主MMIC 83和第二从属MMIC 85的相应的焊球95。因此，第一从属MMIC 84(位于图8中最左侧且在图9和10中部分可见)和第三从属MMIC 56(位于图8中最右侧且在图9和10中不可见)的导电条带71、71’是浮置的(或者被连接到适当的固定电位，例如接地)。
作为上述的备选方案，第一从属MMIC 84和第三从属MMIC 56的导电条带71、71’可以被连接到相应的焊球95，但是这些焊球不被连接到任何金属线，或者如果设想，可能仅连接到公共接地线。
在PCB 92上形成的迹线部分94使得能够将同步线96连接到MMIC 83至86的输入端子LOin和主MMIC 83的输出端子LOout。详细地说，参考图9和图10，通过用95A标识以未示出的方式被耦合到第一从属MMIC 84的输入端子LOin的焊球(在图9和图10中用虚线表示，因为它没有被截面平面穿过)；用95B标识被耦合到主MMIC 83的导电条带71、71’的第一端(在图9和图10中左侧)的焊球；通过95C标识被耦合到主MMIC 83的导电条带71、71’的第二端(在图9和10中的右侧)的焊球；并且通过95D标识被耦合到第二从属MMIC 85的导电条带71、71’的第一端(在图9和10中的左侧)的焊球，第一迹线部分94A将从属MMIC 85的焊球95A连接到主MMIC 83的焊球95B，并连接到以未示出的方式被耦合到主MMIC 83的输入端子LOin的焊球(不可见)；第二迹线部分94B将主MMIC 53的焊球95C连接到第二从属MMIC 85的焊球95D，并连接到以未示出的方式被耦合到主MMIC 83的输出端子LOout的焊球(不可见)；第三迹线部分94C(仅在图8中示出)将第二从属MMIC 85的导电条带71的第二端连接到被耦合到第二从属MMIC 85的输入端子LOin的焊球(不可见)，并连接到第三从属MMIC 86的输入端子LOin焊球。
应该注意的是，该解决方案还可以应用于引线键合/焊球混合技术的情况，这对本领域的技术人员来说是显而易见的。
图11至13示出了实现用于路由同步信号LO的不同解决方案的电子设备100。这里，MMIC具有集成在管芯内的微带或共面波导，并且微带或共面波导在每个管芯的整个宽度上延伸以连接其相对侧。与端子LOin和LOout的连接通过MMIC内部的金属连接线或引线以及在PCB上形成的导电迹线发生。图11和图12中所示的关于通过eWLB技术键合MMIC 83至86的解决方案，还能够用于通过FC-BGA技术或引线键合技术耦合MMIC 83至86的情况，如下文参考图13所述。
详细地说，如图11和图12中所示，其中图8和图9的电子设备70的相同部分由相同的参考数字标示并且不再描述，并且管芯73被表示为由绝缘层105覆盖的半导体基底104形成，每个MMIC 83至86具有金属导电条带101，金属导电条带101在这里由在每个管芯73的绝缘层105内延伸的金属化层形成。每个导电条带101在这里直接在相应的管芯73的表面73A下方形成。在主MMIC 83和第二从属MMIC 85的情况下，每个导电条带101通过在绝缘层105中形成的过孔和接触焊盘103在其各自的端部连接到被布置在每个MMIC 83、85的边缘上的相应的焊球95，以及在介电层72中形成并且与金属连接线71类似的相应的金属连接线102。在第一从属MMIC 84和第三从属MMIC 86的情况下，导电条带101不被电连接到电子设备100的电子元件74，如上文针对导电条带71、71’所述。
实际上，在这种情况下，形成微带或共面波导的导电条带101与元件74一起在晶片级制造，并且当晶片被切割成单独的管芯73时已经存在。
该解决方案此外可以被应用于使用FC-BGA键合技术进行键合的情况(在这种情况下，导电条带101通过如图10中所示的凸块和键合支撑件被电耦合到焊球95)以及被应用于被配置为以低频工作并且提供有通过引线键合(引线键合封装件)被耦合到PCB的封装件的电子设备。
例如，图13示出了具有图11的连接方案的电子设备110，但是其中MMIC通过引线键合连接。因此，与图11和图12的电子设备100相同的元件由相同的参考数字标示并且不再描述。
详细地说，在图13中所示的示例中，每个MMIC 83至86包括将相应的接触焊盘103连接到引脚116的键合引线115。此外在这里，接触焊盘103被布置在导电条带101的相对的端部；每个导电条带101在每个管芯73的绝缘层105内形成并且几乎在其整个宽度上延伸。在图13中，为简单起见，绝缘层105被示为覆盖每个管芯72的半导体基底104并且仅在接触焊盘103处开口的单层。然而，绝缘层105可以以已知方式由在彼此重叠布置的不同层形成。
管芯73和键合引线115由封装层117或包含介电材料(例如，模制树脂)的层覆盖(但是封装层可以根据任何已知的封装技术形成，这对于本领域的技术人员来说是显而易见的)。封装层117还在除了背侧之外的所有侧上嵌入引脚116，在背侧处这些引脚116与同步线96的迹线部分94直接电接触。
如图12中所示，在图13中，主MMIC 83和第二从属MMIC 85的导电条带101仅通过键合引线115连接。因此，第一MMIC 84和第三MMIC 86的导电条带101浮置(或者被连接到适当的固定电位，例如接地)。图13因此用虚线(被布置在与截面平面平行的平面中)示出了将第一从属MMIC 84的输入端子LOin连接到第一迹线部分94A的键合线115，该第一迹线部分94A与主MMIC 83的导电条带101的端部电连接，如上文参考图11所述。
本文描述的MMIC和电子设备具有许多优点。
特别地，所述解决方案允许将由主MMIC生成的同步信号传送到从属MMIC，而不需要PCB方案中的附加连接层，因此成本较低。
所述封装结构允许使用(至少部分地)与天线结构60、61、90、91交换的射频信号的相同导电层携带的同步信号LO。
同步信号LO的路径被简化并且可以被最小化，因此降低了损耗现象或布局复杂性。
最后，很明显，可以对本文描述和示出的集成电路和电子设备进行修改和变更，而不因此背离本公开的范围。例如，所述的不同实施例可以被组合以提供进一步的解决方案。
例如，MMIC还可以彼此不对齐地布置，而只是在RX和TX天线结构之间并排布置。在这种情况下，同步迹线70可以包括折线。
该电子设备可以包括不同类型的集成电路，甚至是在与射频不同的频率下操作。
可以组合上述各种实施例以提供进一步的实施例。可以根据上述详细描述对实施例进行这些和其他变更。通常，在所附权利要求中，所使用的术语不应该被解释为将权利要求限制于说明书和权利要求中公开的特定实施例，而应该被解释为包括所有可能的实施例以及这些权利要求有权获得的等效物的全部范围。因此，权利要求不受本公开的限制。

Claims (20)

1.一种集成电路封装件，其特征在于，包括：
管芯，包括半导体材料和集成电子元件；
连接区域，覆盖在所述管芯上；以及
多个焊球，被固定到所述连接区域并且被电耦合到所述电子元件，所述焊球被布置成阵列并且沿着与一个方向平行的多条线被对齐，
其中所述多条线包括空线，沿着所述空线不存在焊球。
2.根据权利要求1所述的集成电路封装件，其特征在于，第一线以相互均匀的第一距离被布置，并且第一相邻线属于所述多条线并且与所述空线直接相邻，所述第一相邻线以相互的第二距离被布置，所述第二距离大于所述第一距离。
3.根据权利要求2所述的集成电路封装件，其特征在于，所述第二距离是所述第一距离的两倍。
4.根据权利要求1所述的集成电路封装件，其特征在于，所述集成电路封装件是单片微波集成电路封装件。
5.一种电子设备，其特征在于，包括：
支撑件，具有面；
多个集成电路，所述集成电路中的每个集成电路具有集成电子元件；
多个焊球，用于每个集成电路，所述多个焊球被电耦合到相应的所述集成电路的所述电子元件，并且被固定在所述支撑件的所述面与相应的所述集成电路之间；
天线结构，在所述支撑件的所述面上；以及
电连接路径，在所述支撑件的所述面上，并且将所述天线结构电耦合到每个集成电路的所述多个焊球的第一焊球；
其中每个集成电路的所述多个焊球被布置成阵列，并且沿着与一个方向平行的多条线被对齐，
所述多条线包括不存在焊球的空线，以及
导电同步路径在所述支撑件的所述面上延伸，并且被电耦合到每个集成电路的至少第一焊球，所述导电同步路径具有至少第一部分，所述第一部分沿着所述多个集成电路的至少一个集成电路的所述空线延伸。
6.根据权利要求5所述的电子设备，其特征在于，所述导电同步路径被所述多个集成电路中的所述至少一个集成电路的所述焊球横向包围。
7.根据权利要求5所述的电子设备，其特征在于，第一线以相互均匀的第一距离被布置，并且相邻线属于所述多条线并且与所述空线直接相邻，所述相邻线以相互的第二距离被布置，所述第二距离大于所述第一距离。
8.根据权利要求7所述的电子设备，其特征在于，所述第二距离是所述第一距离的长度的两倍。
9.根据权利要求5所述的电子设备，其特征在于：
所述至少一个集成电路形成主集成电路，并且包括输出端子，所述输出端子被耦合到第二焊球并且被配置为生成同步信号；
所述多个集成电路包括第一从属集成电路和第二从属集成电路，所述第一从属集成电路和第二从属集成电路被布置在所述主集成电路的不同侧上；并且
所述导电同步路径具有在所述支撑件的所述面上延伸的连接部分，所述连接部分从所述第一部分分支并且被耦合到所述主集成电路以及所述第一从属集成电路和所述第二从属集成电路这三者的所述第一焊球。
10.根据权利要求9所述的电子设备，其特征在于，所述连接部分包括：第一连接部分，在所述主集成电路与所述第一从属集成电路之间延伸；第二连接部分，在所述主集成电路与所述第二从属集成电路之间延伸；第三连接部分，在所述第一部分与所述主集成电路的相应的第一焊球之间延伸；以及第四连接部分，在所述第二连接部分与所述主集成电路的所述第二焊球之间延伸，所述第三连接部分和所述第四连接部分在所述主集成电路的相对侧上延伸。
11.根据权利要求5所述的电子设备，其特征在于，所述焊球形成倒装芯片球栅阵列耦合或嵌入式晶片级BGA耦合。
12.根据权利要求5所述的电子设备，其特征在于，所述集成电路是单片微波集成电路。
13.根据权利要求5所述的电子设备，其特征在于，所述电子设备是微波雷达设备。
14.一种电子设备，其特征在于，包括：
印刷电路板，具有表面；以及
半导体设备封装件，被物理耦合到所述印刷电路板的所述表面，所述半导体设备封装件包括：
半导体管芯，具有集成电子元件；
连接区域，在所述半导体管芯上；以及
多个焊球，被连接到所述连接区域并且被电耦合到所述电子元件，所述焊球被布置成阵列并且沿着与一个方向平行的多条线对齐，
其中所述多条线包括空线，沿着所述空线不存在焊球。
15.根据权利要求14所述的电子设备，其特征在于，第一线以相互均匀的第一距离被布置，并且第一相邻线属于所述多条线并且与所述空线直接相邻，所述第一相邻线以相互的第二距离被布置，所述第二距离大于所述第一距离。
16.根据权利要求15所述的电子设备，其特征在于，所述第二距离是所述第一距离的两倍。
17.根据权利要求15所述的电子设备，其特征在于，所述半导体设备封装件是单片微波集成电路封装件。
18.根据权利要求15所述的电子设备，其特征在于，所述多个焊球形成倒装芯片球栅阵列耦合或嵌入式晶片级BGA耦合。
19.根据权利要求15所述的电子设备，其特征在于，所述电子设备是微波雷达设备。
20.根据权利要求15所述的电子设备，其特征在于，进一步包括：天线，在所述印刷电路板的所述表面上，并且被电耦合到所述半导体设备封装件。
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