CN215299243U - 具有耦合面的集成电路、电子设备以及具有印刷电路板的设备 - Google Patents
具有耦合面的集成电路、电子设备以及具有印刷电路板的设备 Download PDFInfo
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- CN215299243U CN215299243U CN202120258429.6U CN202120258429U CN215299243U CN 215299243 U CN215299243 U CN 215299243U CN 202120258429 U CN202120258429 U CN 202120258429U CN 215299243 U CN215299243 U CN 215299243U
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Abstract
本公开的实施例涉及具有耦合面的集成电路、电子设备以及具有印刷电路板的设备。该集成电路包括:半导体衬底;集成在半导体衬底中的电子组件;覆盖在半导体衬底上的电连接结构;以及具有细长形状的导电区域,该导电区域具有第一端和第二端。导电区域形成在电连接结构中,在衬底的整个长度上延伸,并且不直接电连接到电子组件。第一同步连接元件和第二同步连接元件分别电耦合到导电区域的第一端和第二端,并且各自具有面对耦合面的相应的同步连接部分。根据本公开的实施例的集成电路使用现有的连接技术,例如基于焊球的技术,克服了现有技术的缺点。
Description
技术领域
本公开涉及一种集成电路、一种电子设备以及具有印刷电路板的设备,电子设备包括通过同步信号而被电耦合的多个集成电路。
背景技术
本公开涉及一种集成电路和一种电子设备,电子设备包括通过同步信号而被电耦合的多个集成电路。
特别地,这种类型的电子设备被用在射频应用中(例如被用在用于机动交通工具的雷达中(通常,在76GHz至81GHz的频率范围内),其中存在许多发射和/或接收通道),和/或被用在例如医疗用途的成像应用中。
在这些类型的多通道应用中,目前,由于MMIC(单片微波集成电路)统一的电气特性(通常地,它们与50Ω的阻抗匹配),这使得它们易于使用,因为它们可以被容易地级联连接,而无需任何外部阻抗匹配网络,所以MMIC(单片微波集成电路)越来越多地被使用。
以该方式,可以制造由多个级联连接的MMIC形成的设备,其中的每个MMIC被配置成管理少量的发射/接收通道。例如,MMIC可以连接在一起,以便第一MMIC(被称为“主机”)生成同步信号,并且将这些信号提供给所有其他MMIC(被称为“从机”)。特别地,主机根据应用(例如,在20GHz、40GHz或80GHz)以或多或少的高频生成同步信号LO。利用这种布置,所有MMIC从主机接收同步信号LO,并且能够使用发射天线连接和接收天线连接以同步的方式发射和接收射频信号。
例如,以该方式,高端雷达设备能够使用三个MMIC(一个主机和两个从机)来管理12个接收通道(在下文被称为“RX通道”)和9个发射通道(在下文被称为“TX通道”),每个MMIC均能够管理四个RX通道和三个TX通道。更一般地,这种类型的雷达设备能够使用M个MMIC来管理X个RX通道和Y个TX通道,每个MMIC 均能够管理X/M个RX通道和Y/M个TX通道。
此外,一般地,用于发射/接收射频信号的基于MMIC的设备包括承载MMIC和天线的印刷电路板(PCB),并且可以具有图1中所示和下文所述的布局。
例如,图1示出了设备1,其包括承载一个主MMIC 3和三个从 MMIC 4-6的印刷电路板(PCB 2)(但是MMIC的数目可以更大或更小)。在图1的俯视平面图中,MMIC 3-6并排设置在接收天线结构(图1上部的RX天线10)和发射天线结构(图1下部的TX天线 11)之间。
高频MMIC 3-6通常被固定到PCB 2并且通过焊球连接电连接在一起,如在下文中更详细地描述的。PCB 2具有:表面电连接13,其通常被形成为PCB 2的表面上的导电轨道,用于将MMIC 3-6电连接到RX天线10和TX天线11;掩埋的电连接14,其由通常在PCB 2 的内部层中延伸的导电轨道形成;以及连接过孔,用于连接PCB 2的不同层级和表面,用于以已知方式在MMIC 3-6之间交换信号和电量并且在图1中仅被示意性示出。
在射频应用中,由于高工作频率(通常高于40GHz),目前通过 FC-BGA(倒装芯片球栅阵列(Flip Chip-Ball Grid Array))技术或 eWLB(嵌入式晶圆级BGA(embedded Wafer-Level BGA))技术来实现焊球连接。
众所周知,两种技术都使用固定在每个MMIC 3-6的要被耦合到 PCB 2的一侧上(例如背侧上)的球栅阵列15,如图2中作为示例所示的,其中焊球由15指定,并且一般MMIC由16指定。
在FC-BGA技术的情况下(参见图3,其是穿过一般MMIC 16 的横截面),焊球15被固定到连接衬底7的一侧,该联接衬底7由容纳电介质材料9的两个板8形成。电介质材料9嵌入金属连接线18,金属连接线18将焊球15与凸块17电连接,凸块17在与焊球15相对的一侧上被固定到连接衬底7。此外,凸块17被固定到容纳电子组件(整体由22指定)的裸片21,并且使得信号和可能的其他电量(例如,供电量,在下文被包括在术语“信号”中)在每个MMIC 3-6的电子组件22与连接衬底7之间通过。电介质填充和匹配层(所谓的底部填充层19)在裸片21和连接衬底7之间延伸并且覆盖凸块17。盖12通过粘合剂层23被键合到连接衬底7,并且围绕裸片21、凸块 17和底部填充层19,以与连接衬底7形成一种封装。
在eWLB技术的情况下(参见图4,其示出了穿过一般MMIC 16 的一部分的横截面),每个焊球15通常被固定到相应的导电区域25。在电介质层26内的导电区域25(仅示出其中一个)通常由铜制成,并且形成一个或多个再分布层(在图4中,示出了单个再分布层RDL24)。电介质层26在钝化层27之上延伸,除了在接触焊盘30处的开口之外,钝化层27覆盖裸片28,接触焊盘30形成在裸片28的表面上,并且电连接到集成在裸片28中的电子组件(整体由31指定)。这里,裸片28被外围区域29围绕。外围区域29通常通过压缩模制来制造,并且加宽了裸片28的面积,使得电介质层26(也在外围区域29之上延伸)可以具有比裸片28更大的面积,使得焊球15能够例如以500μm的间距被布置在比裸片28宽阔的区域上。
eWLB技术允许获得最小的互连长度,并且允许获得上至高频(具有在毫米域中的波长)的非常好的电性能,不需要利用底部填充材料进行底层填充,使得可以具有大量的输入/输出连接,并且具有低成本。
在MMIC 3-6之间交换的信号中间,特别重要的是同步信号LO,因为它可以维持MMIC 3-6之间的相位相干性和放大平衡。
当前,使用PCB 2的内部附加层,同步信号LO(具有两个不同的输入以使能PCB 2中的对称布线)通过掩埋连接14而被路由,因为这些同步连接不能形成在PCB 2的顶层上,以便不使表面电连接 13与RX天线10和TX天线11(图1)交叉。
然而,这导致掩埋连接14的复杂性的增加,并且导致形成PCB 2 的内部附加层的成本高。此外,各个层之间的过渡增加,这导致信号振幅的不期望的下降。
实用新型内容
本公开提供了一种集成电路、一种电子设备以及一种具有印刷电路板的设备,其使用现有的连接技术,例如基于焊球的技术,克服了现有技术的缺点。
根据本公开,提供了一种集成电路、一种电子设备以及一种具有印刷电路板的设备。
在本公开的第一方面,提供了一种具有耦合面的集成电路。集成电路包括:半导体衬底;集成在半导体衬底中的电子组件;覆盖在半导体衬底上的电连接结构;以及具有细长形状的导电区域。导电区域具有第一端和第二端,并且导电区域形成在电连接结构中并且在衬底的整个长度之上延伸。导电区域不直接电连接到电子组件。电连接结构包括多个连接元件,多个连接元件具有面对耦合面的相应的连接部分,并且多个连接元件包括第一同步连接元件和第二同步连接元件。第一同步连接元件和第二同步连接元件分别电耦合到导电区域的第一端和第二端,并且各自具有面对耦合面的相应的同步连接部分。
在一些实施例中,集成电路还包括绝缘层,绝缘层在半导体衬底之上延伸并且与之一起形成裸片,其中电连接结构包括覆盖裸片并且具有一定长度的电介质区域,并且导电区域在大致贯穿电介质区域的长度的情况下在电介质区域内延伸。
在一些实施例中,第一同步连接元件和第二同步连接元件包括第一焊球和第二焊球,第一焊球和第二焊球从电介质区域的相应端突出并且属于球栅阵列键合结构。
在一些实施例中,电介质区域容纳嵌入式晶片级BGA(eWLB) 耦合的至少一个再分布层,并且导电区域形成在再分布层中。
在一些实施例中,集成电路还包括绝缘层,绝缘层在半导体衬底之上延伸并且与之一起形成裸片;导电区域在绝缘层内延伸;并且第一同步连接元件和第二同步连接元件包括金属连接区域,金属连接区域在覆盖或至少部分围绕裸片的电介质区域中延伸,并且与相应的同步连接部分选择性电接触。
在一些实施例中,多个连接元件的连接部分包括属于球栅阵列连接结构的焊球,球栅阵列连接结构形成倒装芯片-球栅阵列(FC-BGA) 耦合或嵌入式晶片级BGA(eWLB)耦合。
在一些实施例中,电介质区域包括封装层,多个连接元件的连接部分包括多个耦合针脚,并且金属连接区域包括导线连接,其中第一同步连接元件和第二同步连接元件包括相应的同步导线元件,同步导线元件耦合在导电区域的相应端与相应的耦合针脚之间。
在一些实施例中,集成电路还包括:同步生成器电路,被配置成生成同步信号;以及输出端子,耦合到同步生成器电路,其中多个连接元件还包括信号连接元件,信号连接元件耦合到输出端子并且具有多个连接部分中的相应的信号连接部分。
在一些实施例中,集成电路是单片微波集成电路。
在一些实施例中,导电区域是由金属材料形成的区域。
在本公开的第二方面,提供了一种电子设备,该电子设备包括:具有支撑面的支撑件;以及多个集成电路,每个集成电路均具有耦合到支撑面的耦合面。集成电路中的每个集成电路包括:集成了电子组件的半导体衬底;覆盖在半导体衬底上的电连接结构;以及形成在电连接结构内的具有细长形状的导电区域。导电区域具有第一端和第二端,在衬底的整个长度之上延伸,并且不直接电连接到电子组件。多个集成电路中的第一集成电路被配置成生成同步信号。每个电连接结构包括多个连接元件。多个连接元件包括信号连接元件,信号连接元件将电子组件电耦合到面对相应耦合面的相应信号连接部分。至少第一集成电路的电连接结构还包括与信号连接元件相邻的第一同步连接元件和第二同步连接元件,第一同步连接元件和第二同步连接元件分别电耦合到相应导电区域的第一端和第二端、具有面对耦合面的相应的同步连接部分并且被配置成路由同步信号。电子组件被键合到支撑面,并且电连接轨道在支撑面上延伸并且将电子组件电耦合到每个集成电路的信号连接元件的信号连接部分。同步导电轨道段在支撑面上延伸、并且将至少第一集成电路的同步连接部分电耦合到集成电路的选择性信号连接部分。
在一些实施例中,电连接结构包括:绝缘层,在半导体衬底之上延伸并且与之一起形成裸片;以及电介质区域,电介质区域在裸片之上延伸并且具有一定长度,其中导电区域在电介质区域内大致延伸电介质区域的整个长度。
在一些实施例中,多个连接元件的连接部分包括属于球栅阵列连接结构的焊球。
在一些实施例中,电连接结构包括:绝缘层,在半导体衬底之上延伸并且与之一起形成裸片;以及电介质区域,覆盖或至少部分围绕裸片,其中导电区域在绝缘层内延伸,以及第一连接元件和第二连接元件在电介质区域中延伸。
在一些实施例中,多个连接元件包括属于球栅阵列连接结构的焊球,球栅阵列连接结构形成倒装芯片球栅阵列耦合或嵌入式晶片级 BGA耦合。
在一些实施例中,多个连接元件中的连接元件包括导线连接,电介质区域包括封装层,信号连接部分和同步连接部分包括多个耦合针脚,并且第一同步连接元件和第二同步连接元件包括相应的导线元件,相应的导线元件耦合在导电区域的相应端与相应的耦合针脚之间。
在一些实施例中,第一集成电路形成主集成电路,多个集成电路至少包括被布置在主集成电路的相对侧上的第一从电路和第二从电路,主集成电路包括输出端子,输出端子耦合到多个信号连接元件中的相应信号连接元件、并且被配置成提供同步信号;以及同步导电轨道段包括在支撑件的面上延伸的连接部分,在支撑件的面上延伸的连接部分在第一从集成电路的信号连接部分和第二从集成电路的信号连接部分与主集成电路的同步连接部分之间、并且在主集成电路的信号连接部分与第一同步连接部分之间。
在本公开的第三方面,提供了一种具有印刷电路板的设备,该设备包括具有表面的印刷电路板(PCB),和物理联接到PCB的表面的半导体设备封装。半导体设备封装包括:半导体衬底;集成在半导体衬底中的电子组件;覆盖半导体衬底的电连接结构;以及具有细长形状的导电区域,导电区域具有第一端和第二端,导电区域形成在电连接结构中,在衬底的整个长度之上延伸,并且不直接电连接到电子组件。电连接结构包括多个连接元件,多个连接元件具有面对耦合面的相应的连接部分。多个连接元件包括第一同步连接元件和第二同步连接元件,并且第一同步连接元件和第二同步连接元件分别电耦合到导电区域的第一端和第二端,并且各自具有面对耦合面的相应的同步连接部分。接收天线物理联接到PCB的表面并且电耦合到半导体设备封装,并且发射天线物理联接到PCB的表面并且电耦合到半导体设备封装。
在一些实施例中,半导体设备封装被布置在接收天线与发射天线之间。
在一些实施例中,半导体设备封装是单片微波集成电路封装。
附图说明
为了更好地理解本公开,现在仅通过非限制性示例的方式,参考附图描述本公开的一些实施例,其中:
图1示出了具有多个用于已知类型的射频应用的集成电路的电子设备的布局;
图2是被配置成使用球栅阵列技术进行键合的集成电路的底部透视图;
图3是被配置成使用FC-BGA技术进行键合的图2的集成电路的一部分的横截面;
图4是被配置成使用eWLB技术进行键合的图2的集成电路的一部分的横截面;
图5示出了根据一个实施例的具有多个集成电路的电子设备的布局;
图6是图5的集成电路的仰视图;
图6A示出了图6的集成电路的放大细节;
图7是图5的集成电路的一部分的横截面;
图8示出了根据另一实施例的具有多个集成电路的电子设备的布局;
图9是沿截线IX-IX截取的图8的电子设备的集成电路的一部分的横截面;
图10是沿与图9相同的截线截取的图9的集成电路的不同实施例;
图11示出了根据不同实施例的具有多个集成电路的电子设备的布局;
图12是沿截线XII-XII截取的图11的电子设备的集成电路的一部分的横截面;以及
图13是沿与图12相同的截线截取的图12的集成电路的不同实施例的横截面。
具体实施方式
图5示出了电子设备50,其包括印刷电路板PCB 52,印刷电路板PCB 52承载四个MMIC,例如,一个主MMIC 53和三个从MMIC 54-56(但是从MMIC的数目可以不同)。在图5的俯视平面图中, MMIC 53-56并排布置在接收天线结构(图5上部的RX天线60)和发射天线结构(图5下部的TX天线61)之间。
参考图7,MMIC 53-56包括容纳电子组件(整体由58示意性地表示和指定)的半导体设备封装57(在一些实施例中,其可以被称为裸片57)。连接区域59在裸片57之上延伸。在eWLB键合技术的情况下,该连接区域由容纳金属连接线61的电介质层形成,如上面参考图4所描述的。在FC-BGA键合技术的情况下,连接区域59由类似于图3的键合支撑件7的键合支撑件形成。在eWLB键合技术的情况下,可能的钝化层在图7中不可见,围绕芯片57的可能的外围区域在图7中也不可见,或者在FC-BGA键合技术的情况下,底部填充层和凸块在图7中不可见,但是它们可以存在,如分别在图4和图 3中所示的。
再次参考图5,MMIC 53-56通过表面电连接63连接到RX天线 60和TX天线61,以已知的方式,表面电连接63形成为在PCB 52 的承载MMIC 53-56的表面上的导电轨道。另外,MMIC 53-56通过在PCB 52中形成的掩埋连接(如下所述)以及也通过同步线64(在下文中详细描述)相互连接,同步线64使得由主MMIC 53生成的同步信号LO路由通过电子组件74,并且同步信号LO以本身已知的方式被提供给从MMIC 54-56以用于它们的同步和振幅平衡。
在下文中,为了更好地理解,从MMIC 54-56也被称为第一、第二和第三从MMIC 54、55和56。在所示的实施例中(特别地,参见图5),主MMIC 53被布置在第一从MMIC 54(位于左侧)和第二从MMIC 55(位于右侧)之间。因此,同步信号LO越过主MMIC 53 和第二从MMIC55。
MMIC 53-56(还参见图6和7)通过使用焊球65的焊球技术被固定和电连接到PCB52。可以使用上文所述和图3和图4中所示的 FC-BGA技术或eWLB技术来键合焊球65。应当注意,在下文中将使用术语“球”,但是,在键合之后,它们通常会变形并且具有不同于球形的形状。
如在图6中可以注意到,焊球65成行和成列布置,在图6中行分别由字母A-Y标识,以及列分别由数字1-18标识,但是在行J上不存在焊球65。
以该方式,行J定义了空行或缺失行,即,布置在相邻行(图6 中的行K和行H)上的焊球65彼此之间以大于其他相邻行的距离的距离布置。特别地,参考图6A的放大细节,如果p表示阵列中相邻行之间的间距(即,属于彼此相邻行的焊球65的中心点之间的距离),则在空行处,距离d是间距p的两倍(d=2p)。
如图6中的虚线所表示的,同步线64在空行中(在PCB 52上) 在以距离d布置的两行焊球65之间延伸。
参考图7,PCB 52以已知的方式包括电介质材料的主体67,主体67具有第一面67A和第二面67B,并且嵌入了导电区域68,导电区域68连接在一起并且通过金属过孔69连接到第一面67A,以用于 MMIC 53-56之间的电连接。可能的过孔(未示出)也可以将导电区域68连接到PCB 52的第二面67B。此外,PCB 52的第一面67A承载表面电连接63(这里不可见)和同步线64。
特别地(也参见图5),同步线64在这里由同步轨道66形成,同步轨道66包括直线部分66A和分支部分66B,分支部分66B从直线部分66A延伸远至布置在MMIC 53-56的端子处的相应焊球65,相应焊球65旨在接收/发射同步信号LO(在图5中,同步信号LO由针对输入端子的LOin和针对输出端子的LOout表示)。例如,连接到焊球65A(其耦合到图5的主MMIC 53的输入端子LOin和输出端子LOout)的分支部分66B在图6中由虚线表示。
实际上,在图5所示的实施例中,即使所有MMIC 53-56具有空行,并且分支部分66B被连接到用于主MMIC 53的两个焊球65(图 6中的焊球65A和65B)和用于MMIC 54-56的单个焊球65,但是同步线64的直线部分66A也仅在主MMIC 53和第二从MMIC 55下方延伸。
然而,直线部分66A不一定由横穿主MMIC 53和第二从MMIC 55 的单个段形成,而是可以由中断的线形成,仅其越过单个MMIC 53 和55的部分优选是线性的。
同步轨道66可以以与形成在PCB 52的第一面67A上的表面电连接63相同的方式形成,例如,形成为铜轨道,并且通常具有比焊球 65小低得多的厚度,即使在这些焊球在焊接之后略微变形时,如图7 中可见的。
图8-图10示出了实现用于路由同步信号LO的不同解决方案的电子设备70。这里,MMIC包括微带(具有被布置在下方的接地区域) 或共面波导(在与波导相同的平面中具有接地区域)。微带或共面波导形成在裸片上方,并且实际上贯穿每个MMIC的宽度延伸,以连接每个MMIC的相对侧。通过形成在PCB上并且通过焊球连接到微带或共面波导的导电轨道获得与端子LOin和LOout的连接。图8和图 9中所示的关于通过eWLB技术对MMIC进行键合的该解决方案,也可以在利用FC-BGA技术对MMIC进行键合的情况下使用,如下所述。
在图8和图9中,MMIC(这里由83-86指定)具有耦合面81,如图4中所示的那样形成,并且每个MMIC均包括集成了电子组件(整体由74指定)、外围区域76和电介质层72的裸片73。如上面参考图4所述,示意性表示的金属连接线75在电介质层72中延伸并且与焊球95连接。此外,为了清楚,这里从MMIC 84-86也被称为第一、第二和第三从MMIC。应当注意,这里,尽管未示出,但是以本身已知的方式,每个裸片73从切割经加工的半导体晶片而得到,并且包括被容纳金属连接线(也未示出)的一个或多个绝缘层(未示出)覆盖的半导体衬底(未示出)。
此外,与图5中一样,在图8中,MMIC 83-86并排布置在接收天线结构RX天线90和发射天线结构TX天线91之间,并且通过形成在PCB(由92指定)上的表面电连接93耦合到RX天线90和TX 天线91,PCB以已知的方式包括电介质材料的主体97,主体97嵌入导电区域98,导电区域98连接在一起并且通过金属过孔99连接到第一面97A。
具体地,关于图8和图9的实施例,每个MMIC 83-86具有形成在主MMIC 83的电介质层72和从MMIC 84-86的电介质层72中的导电带71。
这里,使用再分布层RDL形成导电带71。
图10示出了图9的一种变型,其中MMIC 83-86使用FC-BGA 技术进行键合。
在这里,由70’指定的电子设备在类似于图3的连接衬底7的连接衬底89内具有导电带71’,导电带71’形成在金属层中,该金属层与用于形成金属连接线88(其类似于图3的金属连接线18)的金属层类似。在图10中,未示出板8,并且底部填充层、凸块和盖分别由77、79和80指定。
在图9和图10的两种情况下,导电带71、71’大致贯穿MMIC 83-86的宽度(并且因此贯穿电介质层72的宽度或贯穿连接衬底89 的宽度)延伸,仅在距MMIC 83-86的边缘的较短距离处终止。
应当注意,在该上下文中,术语MMIC 53-56的宽度指示MMIC 53-56在邻接方向上的尺寸。
如图8中所示,电子设备70、70’具有同步线96,同步线96由 MMIC 83-86中的一些(由同步线96越过的那些MMIC)的导电带 71、71’和形成在PCB 92上的轨道部分94形成。形成同步线96的导电带71、71’和轨道部分94通过焊球95连接在一起。
详细地,同步线96在这里由主MMIC 83和第二从MMIC 85(在图9和图10中,布置在主MMIC 83的右侧)的导电带71、71’形成。导电带71、71’不电耦合到组件74中的任何组件,并且仅连接到主 MMIC 83和第二从MMIC 85的相应的焊球95。因此,第一从MMIC 84(在图8中位于最左侧,并且在图9和图10中部分可见)和第三从MMIC 86(在图8中位于最右侧,并且在图9和图10中不可见) 的导电带71、71’浮动(或连接到适当的固定电位,例如地)。
作为上述的备选,第一从MMIC 84和第三从MMIC 86的导电带 71、71’可以连接到相应的焊球95,但是这些导电带71、71’未连接到任何金属线,或者如果需要,可能仅连接到公共地线。
形成在PCB 92上的轨道部分94使得能够将同步线96连接到 MMIC 83-86的输入端子LOin和主MMIC 83的输出端子LOout。详细地,参考图9和图10,通过利用95A标识以未示出的方式耦合到第一从MMIC 84的输入端子LOin的焊球(在图9和图10中用虚线表示,因为它未被截面平面穿过);通过95B标识被耦合到主MMIC 83的导电带71、71’的第一端(在图9和图10的左侧)的焊球;通过95C标识被耦合到主MMIC 83的导电带71、71’的第二端(在图 9和10的右侧)的焊球;并且通过95D标识耦合到第二从MMIC 85 的导电带71、71’的第一端(在图9和图10的左侧)的焊球,第一轨道部分94A将从MMIC 84的焊球95A连接到主MMIC 83的焊球 95B,并且将其连接到以未示出的方式耦合到主MMIC 83的输入端子 LOin的焊球(不可见);第二轨道部分94B将主MMIC 83的焊球95C 连接到第二从MMIC 85的焊球95D,并且将其连接到以未示出的方式耦合到主MMIC 83的输出端子LOout的焊球(不可见);第三轨道部分94C(仅在图8中示出)将第二从MMIC 85的导电带71的第二端连接到如下的焊球(不可见),该焊球被耦合到第二从MMIC 85 的输入端子LOin和第三从MMIC 86的输入端子LOin。
应当注意,对于本领域技术人员明显的是,该解决方案也可以在接线键合/焊球混合技术的情况下被应用。
图11-图13示出了实现用于路由同步信号LO的不同解决方案的电子设备100。这里,MMIC具有集成在裸片内的微带或共面波导,并且微带或共面波导贯穿每个芯片的宽度延伸以连接每个芯片的相对侧。与端子LOin和LOout的连接通过金属连接线、或MMIC内部的导线、以及PCB上形成的导电轨道进行。图11和图12所示的关于通过eWLB技术键合MMIC 83-86的该解决方案,也可以在利用 FC-BGA技术或利用接线键合技术对MMIC 83-86进行耦合的情况下使用,如下文参考图13所讨论的。
详细地,如图11和图12中所示,其中图8和图9的电子设备70 的相同部分由相同的附图标记指定并且不再进一步描述,并且裸片73 被表示为由被绝缘层105覆盖的半导体衬底104形成,每个MMIC 83-86具有金属的导电带101,导电带101这里由在每个裸片73的绝缘层105内延伸的金属化层形成。这里,每个导电带101直接形成在相应裸片73的表面73A的下方。在主MMIC 83和第二从MMIC 85 的情况下,每个导电带101在其自身的端部,通过形成在绝缘层105 中的过孔和连接焊盘103以及相应的金属连接线102(形成在电介质层72中,并且类似于金属连接线71),而连接到被布置在每个MMIC 83、85的边缘上的相应焊球95。在第一和第三从MMIC 84、86的情况下,导电带101未电连接到电子设备100的电子组件74,如上文针对导电带71、71’所讨论的。
实际上,在这种情况下,与组件74一起以晶片级制造形成微带或共面波导的导电带101,并且在晶片被切割成单个裸片73时已经存在。
此外,该解决方案既可以被应用于使用FC-BGA键合技术进行键合的情况(在这种情况下,导电带101通过凸块和键合支撑件被电耦合到焊球95,如图10中所示),又可以被应用于被配置成在低频下工作、并且设置有通过接线键合耦合到PCB的封装(接线键合封装)的电子设备。
例如,图13示出了具有图11的连接方案的电子设备110,但是其中MMIC通过接线键合而被连接。因此,与图11和图12的电子设备100相同的部分由相同的附图标记指定,并且不再进一步描述。
特别地,在图13所示的示例中,每个MMIC 83-86包括将相应的接触焊盘103连接到针脚116的键合线115。同样,在这里,接触焊盘103被布置在导电带101的相对端;每个导电带101形成在每个裸片73的绝缘层105内,并且实际上贯穿每个裸片73宽度延伸。在图 13中,为简单起见,绝缘层105被示为单层,该单层覆盖每个裸片 72的半导体衬底104、并且仅在接触焊盘103处敞开。然而,绝缘层 105可以以已知的方式由布置在彼此之上的不同层形成。
裸片73和键合线115被封装层117或包含电介质材料(例如模制树脂)的层覆盖(但是,封装层可以根据任何已知的封装技术形成,这对于本领域技术人员来说是明显的)。封装层117在除了背面之外的所有侧面上还嵌入针脚116,在这些侧面,针脚116与同步线96的轨道部分94直接电接触。
与图12中一样,在图13中,仅主MMIC 83的导电带101和第二从MMIC 85的导电带101通过键合线115连接。因此,第一和第三MMIC 84、86的导电带101浮置(或连接到适当的固定电位,例如地)。因此,图13以虚线示出(因为布置在与截面平面平行的平面中)键合线115,键合线115将第一从MMIC 84的输入端子LOin 连接到第一轨道部分94A,第一轨道部分94A与主MMIC 83的导电带101的一端电连接,如上面参考图11所描述的。
本文描述的MMIC和电子设备具有许多优点。
特别地,所描述的解决方案允许由主MMIC生成的同步信号被运载到从MMIC,而在PCB方案中不需要附加的连接层级,因此成本较低。
所描述的封装结构允许使用(至少部分地)与天线结构60、61、 90、91交换的射频信号的相同传导层来运载同步信号LO。
同步信号LO的路径被简化并且可以最小化,从而减少了损耗现象或布局复杂性。
最后,清楚的是,在不脱离本公开的范围的情况下,可以对本文所述和所示的集成电路以及电子设备进行修改和变化。例如,所描述的不同实施例可以被组合以便提供另外的解决方案。
例如,MMIC也可以被布置成不彼此对齐,而是简单地并排布置在RX和TX天线结构之间。在这种情况下,同步轨道70可以包括中断的线。
电子设备可以包括不同类型的集成电路,该集成电路甚至以与无线电频率不同的频率操作。
上述各种实施例可以被组合以提供另外的实施例。可以根据以上详细描述对实施例进行这些和其他改变。通常,在以下权利要求中,所使用的术语不应当被解释为将权利要求限制为说明书和权利要求中公开的特定实施例,而是应当被解释为包括所有可能的实施例以及赋予这些权利要求的等同物的全部范围。因此,权利要求不受公开内容的限制。
Claims (20)
1.一种具有耦合面的集成电路,其特征在于,所述集成电路包括:
半导体衬底;
电子组件,集成在所述半导体衬底中;
电连接结构,覆盖所述半导体衬底;以及
导电区域,具有细长形状,具有第一端和第二端,所述导电区域形成在所述电连接结构中,在所述衬底的整个长度上延伸,并且不直接电连接到所述电子组件,
其中所述电连接结构包括多个连接元件,所述多个连接元件具有面对所述耦合面的相应的连接部分,所述多个连接元件包括第一同步连接元件和第二同步连接元件,所述第一同步连接元件和所述第二同步连接元件分别电耦合到所述导电区域的所述第一端和所述第二端,并且各自具有面对所述耦合面的相应的同步连接部分。
2.根据权利要求1所述的集成电路,其特征在于,所述集成电路还包括绝缘层,所述绝缘层在所述半导体衬底之上延伸并且与之一起形成裸片,
其中所述电连接结构包括覆盖所述裸片并且具有一定长度的电介质区域,并且所述导电区域在大致贯穿所述电介质区域的所述长度的情况下在所述电介质区域内延伸。
3.根据权利要求2所述的集成电路,其特征在于,所述第一同步连接元件和所述第二同步连接元件包括第一焊球和第二焊球,所述第一焊球和所述第二焊球从所述电介质区域的相应端突出并且属于球栅阵列键合结构。
4.根据权利要求3所述的集成电路,其特征在于,所述电介质区域容纳嵌入式晶片级BGA耦合的至少一个再分布层,并且所述导电区域形成在所述再分布层中。
5.根据权利要求1所述的集成电路,其特征在于,所述集成电路还包括绝缘层,所述绝缘层在所述半导体衬底之上延伸并且与之一起形成裸片;所述导电区域在所述绝缘层内延伸;并且所述第一同步连接元件和所述第二同步连接元件包括金属连接区域,所述金属连接区域在覆盖或至少部分围绕所述裸片的电介质区域中延伸,并且与所述相应的同步连接部分选择性电接触。
6.根据权利要求5所述的集成电路,其特征在于,所述多个连接元件的所述连接部分包括属于球栅阵列连接结构的焊球,所述球栅阵列连接结构形成倒装芯片-球栅阵列耦合或嵌入式晶片级BGA耦合。
7.根据权利要求5所述的集成电路,其特征在于,所述电介质区域包括封装层,所述多个连接元件的所述连接部分包括多个耦合针脚,并且所述金属连接区域包括导线连接,其中所述第一同步连接元件和所述第二同步连接元件包括相应的同步导线元件,所述同步导线元件耦合在所述导电区域的相应端与相应的耦合针脚之间。
8.根据权利要求1所述的集成电路,其特征在于,所述集成电路还包括:
同步生成器电路,被配置成生成同步信号;以及
输出端子,耦合到所述同步生成器电路,
其中所述多个连接元件还包括信号连接元件,所述信号连接元件耦合到所述输出端子并且具有多个所述连接部分中的相应的信号连接部分。
9.根据权利要求1所述的集成电路,其特征在于,所述集成电路是单片微波集成电路。
10.根据权利要求1所述的集成电路,其特征在于,所述导电区域是由金属材料形成的区域。
11.一种电子设备,其特征在于,所述电子设备包括:
支撑件,具有支撑面;
多个集成电路,每个集成电路具有耦合到所述支撑面的耦合面,并且每个集成电路包括:
半导体衬底,集成了电子组件;
电连接结构,覆盖所述半导体衬底;以及
导电区域,具有细长形状,形成在所述电连接结构内,所述导电区域具有第一端和第二端,在所述衬底的整个长度之上延伸并且不直接电连接到所述电子组件,
其中:
所述多个集成电路中的第一集成电路被配置成生成同步信号,以及
每个电连接结构包括多个连接元件,所述多个连接元件包括信号连接元件,所述多个连接元件将所述电子组件电耦合到面对相应耦合面的相应信号连接部分,以及
至少所述第一集成电路的所述电连接结构还包括与所述信号连接元件相邻的第一同步连接元件和第二同步连接元件,所述第一同步连接元件和所述第二同步连接元件分别电耦合到相应导电区域的所述第一端和所述第二端、具有面对所述耦合面的相应的同步连接部分并且被配置成路由所述同步信号;
电子组件,被键合到所述支撑面;
电连接轨道,在所述支撑面上延伸、并且将所述电子组件电耦合到每个集成电路的所述信号连接元件的所述信号连接部分;以及
同步导电轨道段,在所述支撑面上延伸并且将至少所述第一集成电路的所述同步连接部分电耦合到所述集成电路的选择性信号连接部分。
12.根据权利要求11所述的电子设备,其特征在于,所述电连接结构包括:
绝缘层,在所述半导体衬底之上延伸并且与之一起形成裸片;以及
电介质区域,所述电介质区域在所述裸片之上延伸并且具有一定长度,
其中所述导电区域在所述电介质区域内大致延伸所述电介质区域的整个长度。
13.根据权利要求12所述的电子设备,其特征在于,所述多个连接元件的所述连接部分包括属于球栅阵列连接结构的焊球。
14.根据权利要求11所述的电子设备,其特征在于,所述电连接结构包括:
绝缘层,在所述半导体衬底之上延伸并且与之一起形成裸片;以及
电介质区域,覆盖或至少部分围绕所述裸片,
其中所述导电区域在所述绝缘层内延伸,以及
所述第一同步连接元件和所述同步第二连接元件在所述电介质区域中延伸。
15.根据权利要求14所述的电子设备,其特征在于,所述多个连接元件包括属于球栅阵列连接结构的焊球,所述球栅阵列连接结构形成倒装芯片球栅阵列耦合或嵌入式晶片级BGA耦合。
16.根据权利要求14所述的电子设备,其特征在于,所述多个连接元件中的所述连接元件包括导线连接,所述电介质区域包括封装层,所述信号连接部分和所述同步连接部分包括多个耦合针脚,并且所述第一同步连接元件和所述第二同步连接元件包括相应的导线元件,所述相应的导线元件耦合在所述导电区域的相应端与相应的耦合针脚之间。
17.根据权利要求11所述的电子设备,其特征在于:
所述第一集成电路形成主集成电路,
所述多个集成电路至少包括被布置在所述主集成电路的相对侧上的第一从电路和第二从电路,
所述主集成电路包括输出端子,所述输出端子耦合到所述多个信号连接元件中的相应信号连接元件、并且被配置成提供所述同步信号;以及
所述同步导电轨道段包括在所述支撑件的所述面上延伸的连接部分,在所述支撑件的所述面上延伸的所述连接部分在所述第一从集成电路的所述信号连接部分和所述第二从集成电路的所述信号连接部分与所述主集成电路的所述同步连接部分之间、并且在所述主集成电路的所述信号连接部分与第一同步连接部分之间。
18.一种包括印刷电路板的设备,其特征在于,所述包括印刷电路板的设备包括:
所述印刷电路板,具有表面;
半导体设备封装,物理联接到所述印刷电路板的所述表面,所述半导体设备封装包括:
半导体衬底;
电子组件,集成在所述半导体衬底中;
电连接结构,覆盖所述半导体衬底;以及
导电区域,具有细长形状,具有第一端和第二端,所述导电区域形成在所述电连接结构中,并且在所述衬底的整个长度上延伸,并且不直接电连接到所述电子组件,
其中所述电连接结构包括多个连接元件,所述多个连接元件具有面对耦合面的相应的连接部分,所述多个连接元件包括第一同步连接元件和第二同步连接元件,所述第一同步连接元件和所述第二同步连接元件分别电耦合到所述导电区域的所述第一端和所述第二端,并且各自具有面对所述耦合面的相应的同步连接部分;
接收天线,物理联接到所述印刷电路板的所述表面并且电耦合到所述半导体设备封装;以及
发射天线,物理联接到所述印刷电路板的所述表面并且电耦合到所述半导体设备封装。
19.根据权利要求18所述的设备,其特征在于,所述半导体设备封装被布置在所述接收天线与所述发射天线之间。
20.根据权利要求18所述的设备,其特征在于,所述半导体设备封装是单片微波集成电路封装。
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Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3534501B2 (ja) | 1995-08-25 | 2004-06-07 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6057600A (en) | 1997-11-27 | 2000-05-02 | Kyocera Corporation | Structure for mounting a high-frequency package |
US6770955B1 (en) * | 2001-12-15 | 2004-08-03 | Skyworks Solutions, Inc. | Shielded antenna in a semiconductor package |
JP3657246B2 (ja) | 2002-07-29 | 2005-06-08 | Necエレクトロニクス株式会社 | 半導体装置 |
US20050002167A1 (en) | 2003-07-02 | 2005-01-06 | John Hsuan | Microelectronic package |
US20070141751A1 (en) | 2005-12-16 | 2007-06-21 | Mistry Addi B | Stackable molded packages and methods of making the same |
US7915081B2 (en) | 2006-03-31 | 2011-03-29 | Intel Corporation | Flexible interconnect pattern on semiconductor package |
US8860178B2 (en) | 2006-07-03 | 2014-10-14 | Renesas Electronics Corporation | Semiconductor device having an inductor |
US8278749B2 (en) | 2009-01-30 | 2012-10-02 | Infineon Technologies Ag | Integrated antennas in wafer level package |
US8451618B2 (en) | 2010-10-28 | 2013-05-28 | Infineon Technologies Ag | Integrated antennas in wafer level package |
JP5417389B2 (ja) | 2011-07-13 | 2014-02-12 | 株式会社東芝 | 無線装置 |
JP5839267B2 (ja) | 2011-09-28 | 2016-01-06 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US8648454B2 (en) * | 2012-02-14 | 2014-02-11 | International Business Machines Corporation | Wafer-scale package structures with integrated antennas |
US8866292B2 (en) | 2012-10-19 | 2014-10-21 | Infineon Technologies Ag | Semiconductor packages with integrated antenna and methods of forming thereof |
JP6263948B2 (ja) * | 2013-10-17 | 2018-01-24 | 住友電気工業株式会社 | 電極パッド構造 |
US9537199B2 (en) | 2015-03-19 | 2017-01-03 | International Business Machines Corporation | Package structure having an integrated waveguide configured to communicate between first and second integrated circuit chips |
KR102049724B1 (ko) * | 2015-08-18 | 2019-11-28 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
JP6643714B2 (ja) * | 2016-03-10 | 2020-02-12 | 富士通株式会社 | 電子装置及び電子機器 |
US10128192B2 (en) * | 2016-07-22 | 2018-11-13 | Mediatek Inc. | Fan-out package structure |
DE102019106030A1 (de) * | 2018-03-22 | 2019-09-26 | Infineon Technologies Ag | Radar-system mit mehreren radar-chips |
US11791312B2 (en) | 2018-12-04 | 2023-10-17 | Qorvo Us, Inc. | MMICs with backside interconnects for fanout-style packaging |
US11557545B2 (en) * | 2018-12-04 | 2023-01-17 | Qorvo Us, Inc. | Monolithic microwave integrated circuit (MMIC) with embedded transmission line (ETL) ground shielding |
US11296670B2 (en) * | 2020-01-23 | 2022-04-05 | Qualcomm Incorporated | Impedance matching transceiver |
IT202000001819A1 (it) * | 2020-01-30 | 2021-07-30 | St Microelectronics Srl | Circuito integrato e dispositivo elettronico comprendente una pluralita' di circuiti integrati accoppiati elettricamente tramite un segnale di sincronizzazione |
KR20220163438A (ko) * | 2020-04-03 | 2022-12-09 | 울프스피드, 인크. | 게이트 및/또는 드레인에 대한 탄화규소 관통 비아들을 갖는 트랜지스터 다이를 사용하는 적층형 rf 회로 토폴로지 |
KR20220162147A (ko) * | 2020-04-03 | 2022-12-07 | 울프스피드, 인크. | 후면측 소스, 게이트 및/또는 드레인 단자들을 갖는 iii족 질화물계 라디오 주파수 증폭기들 |
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2020
- 2020-01-30 IT IT102020000001822A patent/IT202000001822A1/it unknown
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2021
- 2021-01-26 US US17/158,776 patent/US11854954B2/en active Active
- 2021-01-26 EP EP21153514.1A patent/EP3869555A3/en active Pending
- 2021-01-29 CN CN202120258429.6U patent/CN215299243U/zh active Active
- 2021-01-29 CN CN202110127528.5A patent/CN113270395A/zh active Pending
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US20210242116A1 (en) | 2021-08-05 |
CN113270395A (zh) | 2021-08-17 |
EP3869555A3 (en) | 2021-12-01 |
EP3869555A2 (en) | 2021-08-25 |
IT202000001822A1 (it) | 2021-07-30 |
US11854954B2 (en) | 2023-12-26 |
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