CN1967792A - 制造带有掩埋沟道的鳍式场效应晶体管的结构和方法 - Google Patents

制造带有掩埋沟道的鳍式场效应晶体管的结构和方法 Download PDF

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CN1967792A
CN1967792A CNA2006101429791A CN200610142979A CN1967792A CN 1967792 A CN1967792 A CN 1967792A CN A2006101429791 A CNA2006101429791 A CN A2006101429791A CN 200610142979 A CN200610142979 A CN 200610142979A CN 1967792 A CN1967792 A CN 1967792A
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朱慧珑
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Abstract

一种制造鳍片结构的方法，该方法包括在晶片上形成第一材料类型的第一结构，以及在第一结构侧壁的附近形成第二材料类型掩埋沟道。该第二材料与第一材料不同。该结构包括第一个结构和掩埋沟道。

Description

制造带有掩埋沟道的鳍式 场效晶体管的结构和方法
技术领域
本发明总体上涉及半导体结构和制造方法，更具体地涉及带有掩埋沟道的pFinFET和制造方法。
背景技术
鳍式场效晶体管(FinFET)是形成在SOI/体型半导体衬底上的MOSFET双栅极晶体管。在实施中，栅极被裹在场效应晶体管(FET)沟道周围，形成双栅极结构。FinFET器件显著地能更好的控制短沟道效应，其电流密度大于或者等于传统的CMOS技术，几乎可以用于所有的集成电路的设计(即，微处理器、存储器等)。
特别地，双栅极的使用抑制了短沟道效应(SCE)，使泄漏减少，提供了更为理想的开关行为，从而降低了功率消耗。此外，双栅极的使用增加了栅极的面积，这允许FinFET具有更好的电流控制，而无需增加器件的栅极长度。因此FinFET能够拥有较大晶体管的电流控制能力，而无需要求较大晶体管的器件空间。
在制造过程中，高质量的硅上驰豫SiGe层导致证实具有增强的载流子沟道的FET。并且，在沟道中使用锗可以提高空穴沟道迁移率。尽管在短沟道FET内部载流子散射物理还不为人所知，但是公知，增强的迁移率转换为更好的器件性能，即使栅极很短。
为了提高迁移率，掩埋沟道可以用于单栅极MOSFET。掩埋沟道可以使载流子远离栅极电介质界面的散射，从而提高载流子迁移率或MOSFET性能。然而，由于部分损失了栅极对沟道电势的控制，有掩埋沟道的MOSFET的SCE比传统的MOSFET要差。希望使用针对掩埋沟道MOSFET的双栅极结构，从而获得高性能和良好的SCE，因为双栅极MOSFET给出良好的SCE。
发明内容
本发明的第一方面，制造鳍式结构的方法包括在晶片上形成第一材料类型的第一结构和在第一结构的侧壁附近形成第二材料类型的掩埋沟道。第一材料类型与第二材料类型不同。
本发明的另一方面，形成一种结构的方法包括在含第一材料类型的晶片上形成第一结构和在第一结构的至少一个侧壁附近形成第二材料类型的第二结构。该方法进一步包括在第一结构和第二结构中的一个上形成覆盖层，从而形成前置栅极和后置栅极。
在本发明的另一方面，鳍式结构包括晶片上第一材料的第一垂直结构和与第一结构侧壁相邻的第二材料类型的掩埋沟道。第二材料类型与第一材料类型不同。
附图简述
图1-图8示出按照本发明形成结构的工艺步骤的实施例；
图9示出使用按照本发明工艺的栅极的横截面图；
图10示出按照本发明将前置栅极和后置栅极分开的工艺；
图11示出按照发明得到的最终结构；
图12示出按照本发明的一个替代实施例；
图13和图14示出按照本发明形成结构的另一个实施例。
具体实施方式
本发明涉及一种半导体结构及其制造方法，更具体地涉及带掩埋沟道的FinFET器件及其制造方法。在一个实施例中，本发明的结构提高了迁移率从而显著增强pMOSFET的操作频率和性能。此外，通过使用这种制造方法并因此形成本发明的最终结构，栅极可以更为精确地对沟道进行控制，并通过使载流子远离粗糙的栅极电介质界面从而提高载流子的迁移率，同时控制源极附近的速率过冲。在一个实施过程中，可以本发明的制造工艺控制沟道中掩埋SiGe层的厚度，从而获得本发明的有利结果。
参考图1，其示出起始结构，该结构包括在BOX 10(掩埋氧化物)上形成的硅鳍片12。在该硅鳍片12上形成氮化物硬掩膜14。硅鳍片12和氮化物硬掩膜14是用传统工艺形成的。例如，硅层可以黏合到BOX以及氮化物膜，可以沉积在硅上。然后，可以对氮化物膜构图并使用反应性离子刻蚀(RIE)工艺，以形成氮化物硬掩膜14。也可以使用传统RIE工艺对硅层进行刻蚀，在BOX 10上终止。
图2示出角度注入工艺。在这一工艺中，锗(Ge)被注入到图1中形成的结构的一侧。在一个实施例中，角度注入工艺可以在结构的两侧进行，如下面详细论述。角度注入工艺是在一个角度上执行的，该角度范围大约为45度；然而，本发明也包括其他角度注入工艺。在一个实施例中，注入能量大约为10KeV到30KeV。注入工艺的剂量约为5e14到3e15/cm3。在一个实施例中优选使用锗，因为随后的蚀刻步骤对锗具有选择性。
图3示出除去图2中的注入工艺所引起的锗注入损伤的退火步骤。在图3中，退火工艺发生的温度范围是800摄氏度到1000摄氏度，尽管其他退火温度也包括在本发明考虑范围之内。
在图4中，掺锗硅鳍片12可以通过对硅具有选择性的蚀刻工艺进行蚀刻。譬如，蚀刻可以包括CF4/CH2F2或者CF4/O2。本发明还考虑到硅鳍片12的掺锗部分可用对硅具有选择性的RIE工艺或者其他干法蚀刻工艺进行蚀刻。根据锗注入的深度，掺锗硅鳍片12蚀刻范围约100到200。
在图5中，外延SiGe膜16沉积或生长在硅鳍片12上。在一个实施例中，SiGe膜16仅对硅具有选择性，使得SiGe仅在硅鳍片12上沉积或者生长。应该理解SiGe膜16的基体与硅鳍片12的基体不同。在一个实施例中，SiGe膜16的厚度范围在20到50。SiGe膜16可以用任何传统工艺形成，譬如，CVD。SiGe将形成掩埋沟道，并且在实施例中被用来提高FinFET沟道的沟道迁移率。
在图6中，因为硅鳍片12侧壁上的SiGe没有被氮化物硬掩膜覆盖，可以使用各向异性蚀刻工艺对该侧壁上的SiGe进行有选择的蚀刻。该蚀刻工艺在FinFET的沟道中留下了SiGe膜16。
图7示出在SiGe层16上形成外延Si层18。硅层18的厚度范围在，例如2nm到5nm。在该结构中，SiGe膜16现在被夹在硅鳍片2和硅膜18之间，从而形成带隙结构的基础。
图8示出栅极氧化工艺。特别地，使用传统工艺将栅极氧化膜20沉积在图7的结构的侧面。在一个实施工艺中，高k电介质可以用作栅极电介质，诸如，HfO2，ZrO2，Al2O3，TiO2，La2O3，SrTiO3，LaAlO3和它们的混合物。在本步骤之后，可以使用传统FinFET工艺形成FinFET。例如，可以对多晶硅层进行沉积、蚀刻从而形成栅极，进行角度注入工艺形成扩展区和晕轮区(halo region)。然后，(作为一个例子)可提供通过SD注入和退火工艺形成的间隔件来形成该结构。
图9表示完成图8的工艺之后栅极的横截面。在图9中，栅极氧化物的一面形成前置栅极22，优选是带有掩埋SiGe层18的面。该栅极氧化物另一面形成后置栅极24。在该结构上提供了掺杂多晶硅栅极。
图10示出根据本发明将前置栅极22和后置栅极24分开的工艺。在该工艺中，氧化物26在图9中的结构上沉积。在图11中，作为最终结构，使用化学机械抛光(CMP)将氧化物26磨光，在氮化物硬掩膜14之顶上停止，以将前置栅极22和后置栅极24分开。
如应该理解的那样，后置栅极24被用来调节器件阈值电压，前置栅极22被用来控制器件电流。并且，通过控制从而对锗注入和SiGe外延工艺，进而对随后选择性蚀刻工艺的深度的调节，也可以使用本发明工艺控制掩埋沟道(譬如，SiGe掩埋层)的厚度。这为制造工艺提供了灵活性，从而使SiGe层距离栅极本身更近，以便栅极控制。
参考图12，在可替换工艺中，锗注入工艺可以在该结构的两面进行，从而形成对称的FinFET。角度注入工艺是以一定角度进行的，该角度范围大约为45度；然而，本发明也考虑包括其他角度注入工艺。在一个实施例中，注入能量大约为10KeV到30KeV。该注入工艺的剂量为1e15到3e15/cm3。在一个实施例中优选使用锗，因为随后的蚀刻步骤对锗具有选择性，以便控制。
在图12的实施例中，退火工艺被用来将结构两面上由注入工艺造成的锗注入损伤除去。然后，可以对硅鳍片12进行对锗具有选择性的蚀刻，可以在两面进行干法蚀刻或者湿法蚀刻从而形成对称的结构。根据上述标准，在硅鳍片12的两面沉积或者生长外延SiGe膜18。随后沉积外延硅层20，从而将SiGe膜18夹在中间。外延硅层20的范围可以在约1-2nm。使用传统工艺将栅极氧化物膜20沉积在该结构的两面。在一个实施工艺中，高k电介质可以用作栅极电介质，诸如，HfO2，ZrO2，Al2O3，TiO2，La2O3，SrTiO3，LaAlO3和它们的混合物。在本步骤之后，可以使用传统FinFET工艺形成FinFET。如上所述，可以按照本发明将前置栅极22和后置栅极24分开。
图13和图14示出用于根据本发明形成结构的工艺步骤的另一个实施例。在该实施例的结构中，BOX 10上形成了驰豫SiGe鳍片26。根据一个实例，驰豫SiGe层和氮化物膜可以分别沉积在BOX 10上。然后，可以对氮化物膜进行构图和使用反应性离子刻蚀(RIE)工艺刻蚀从而形成氮化物硬掩膜14。也可以使用传统RIE工艺对SiGe层进行刻蚀，在BOX 10上停止，从而形成驰豫的SiGe鳍片26。
在图14中，在驰豫SiGe鳍片上可以生长外延薄应变硅层28。该外延硅层对SiGe膜具有选择性，可以是驰豫的SiGe鳍片26的侧壁上的厚度大约为2nm到5nm的薄层。在硅层28形成之后，如上所述，可以使用传统工艺步骤形成FinFET，譬如，从图8中的工艺步骤开始。
虽然本发明参考示例性实施例进行了描述，应理解，此处所用的语言应理解为描述性和说明性语言，而不是限制性语言。在不偏离本发明的范围或精神的前提下，可以在所附权利要求的范围内做出变更。因此，尽管根据具体的材料和实施例对本发明进行了描述，本发明的范围并不仅限于此处所披露的细节；相反，本发明包括诸如所附权利要求书范围内的功能等同结构、方法和用途。

Claims (20)

1.一种制造鳍片结构的方法，包括在晶片上形成第一材料类型的第一结构和相邻所述第一结构侧壁形成第二材料类型的掩埋沟道，所述第二材料类型和第一材料类型不同。
2.如权利要求1所述的方法，
其中形成第一结构包括形成第一材料类型的鳍片；以及
其中形成所述掩埋沟道包括：
将第一类型的原子注入到所述鳍片的侧壁中；
选择性修整鳍片的侧壁以形成至少一个底切；
通过在该至少一个底切内沉积或生长第二材料类型，并在该第二材料类型上形成外延层，从而在该至少一个底切内形成掩埋沟道。
3.如权利要求2中所述的方法，进一步包括：
在外延层上形成栅极氧化物或者高k电介质从而形成前置栅极和后置栅极电介质；
在掺杂多晶硅栅极上沉积氧化物；以及
刻蚀氧化物至掺杂多晶硅栅极。
4.如权利要求2所述的方法，其中第一类型原子是锗(Ge)，修整步骤是对硅有选择性的掺锗硅进行蚀刻。
5.如权利要求2所述的方法，其中第二材料类型是外延SiGe膜，其沉积或生长的范围是20到50。
6.如权利要求2所述的方法，其中所述注入工艺是在约10KeV到30KeV的注入能量下执行的，剂量范围约5e14到3e15/cm3。
7.如权利要求2所述的方法，还包括退火从而除去注入工艺造成的注入损伤，退火是在约800摄氏度到1100摄氏度的范围执行的。
8.如权利要求2所述的方法，其中修整是湿法蚀刻工艺或干法蚀刻工艺，该刻蚀工艺是刻蚀对纯硅具有选择性的掺锗硅。
9.如权利要求2所述的方法，进一步包括：
在侧壁上形成外延层；
在所述外延层上形成栅极氧化物或者高k电介质从而形成前置栅极和后置栅极；
形成掺杂的多晶硅栅极；
在该掺杂的多晶硅栅极上沉积氧化物；以及
蚀刻该氧化物至掺杂多晶硅栅极。
10.如权利要求2所述的方法中，其中：
注入和修整是在鳍片的两面进行的从而在鳍片的两面形成底切部分；
通过在与鳍片的两面相邻的底切部分内形成不同的材料类型，和在所述底切部分内不同材料类型上形成外延层而提供掩埋的沟道。
11.如权利要求10所述的方法，其中所述掩埋沟道包含SiGe。
12.如权利要求1所述的方法，其中所述掩埋沟道被控制在一定的深度。
13.如权利要求1所述的方法，其中形成所述第一结构包括在掩埋沟道的侧壁上形成第一材料类型。
14.如权利要求1所述的方法，其中所述掩埋沟道是通过在至少一个底切内和邻近所述第一结构的侧壁形成不同的材料类型，并且在所述掩埋沟道上形成外延层而形成。
15.形成一种结构的方法，其包括：
在包含第一材料类型的晶片上形成第一结构；
在邻近所述第一结构的至少一个侧壁形成第二材料类型的第二结构；以及
在所述第一结构和第二结构之一上形成一个层，从而形成前置栅极和后置栅极。
16.如权力要求15所述的方法，其中所述第二材料类型是在所述第一结构的至少一个侧壁上沉积或生长的外延SiGe膜。
17.如权利要求15所述的方法，还包括：
向所述第一结构的至少一个侧壁内注入第一类型掺杂剂；
选择地修整所述第一结构的至少一个侧壁从而形成至少一个底切；以及
通过在该至少一个底切内形成第一结构，并且在所述侧壁和掩埋沟道上形成外延层，而在该至少一个底切内形成掩埋沟道。
18.如权利要求15所述的方法，其中所述第一材料类型是在所述第二结构侧壁上形成的硅。
19.一种鳍片结构，包括在晶片上的第一材料类型的第一垂直结构，和与所述第一结构的侧壁相邻的第二材料类型的掩埋沟道，所述第二材料类型与第一材料类型不同。
20.如权利要求19所述的鳍片结构，其中一条掩埋沟道是SiGe，且第一材料类型是硅。
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