CN1956196A - biCMOS器件及biCMOS器件的制造方法 - Google Patents

biCMOS器件及biCMOS器件的制造方法 Download PDF

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CN1956196A
CN1956196A CNA2006101428981A CN200610142898A CN1956196A CN 1956196 A CN1956196 A CN 1956196A CN A2006101428981 A CNA2006101428981 A CN A2006101428981A CN 200610142898 A CN200610142898 A CN 200610142898A CN 1956196 A CN1956196 A CN 1956196A
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高光永
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DB HiTek Co Ltd
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Abstract

本发明公开一种包括双极晶体管和多晶硅/绝缘体/多晶硅电容器的biCMOS器件。该biCMOS器件在双极晶体管处可具有相对较低的串联电阻。该双极晶体管可具有理想的放大率。

Description

biCMOS器件及biCMOS器件的制造方法
本申请要求韩国专利申请No.10-2005-0102125(申请日为2005年10月28日)的优先权，该申请的全部内容通过参考援引于此。
技术领域
本发明涉及一种biCMOS器件及biCMOS器件的制造方法
背景技术
biCMOS器件可具有高速度、低功耗和高集成度。biCMOS器件为包括双极晶体管和CMOS晶体管的器件(例如芯片)。biCMOS器件可具有CMOS晶体管的低功耗特性和高集成度特性以及双极晶体管的高速开关特性和高电流驱动性能。
现有多种双极晶体管制造方法适用于biCMOS技术。这些方法可进行优化以与CMOS晶体管制造方法兼容，同时保持高速开关特性和高电流驱动性能。可能需要将多晶硅/绝缘体/多晶硅(PIP)电容器集成在biCMOS器件上并与双极晶体管相邻。可通过高集成技术来实现将双极晶体管和PIP电容器都集成在biCMOS器件上。
例如，图1A至1D为示出具有双极晶体管和PIP电容器的biCMOS器件的制造方法的横截面图。如图1A所示，P型半导体衬底10包括PIP电容器区A和双极晶体管区B。半导体衬底10包括形成在双极晶体管区B中的掩埋层12(例如掺有N型材料)。在掩埋层12上可形成外延层(未示出)。在外延层(未示出)中可形成彼此相邻的第一阱区14a(例如掺有N型材料)和第二阱区14b(例如掺有P型材料)。
场绝缘层16可形成在PIP电容器区A和双极晶体管区B的表面上方。第一多晶硅层18可形成在场绝缘层16上方。光致抗蚀剂层(未示出)可形成在第一多晶硅层18上方。由光致抗蚀剂层可形成掩模图案19(例如用于离子注入)。
如图1B所示，通过将离子注入第一多晶硅层18的暴露区域执行使用掩模图案19的离子注入工艺，以形成掺杂的第一多晶硅层18a。如图1C所示，除去掩模图案19。将第一多晶硅层18图案化，从而只保留掺杂的第一多晶硅层18。第一多晶硅层18a可成为PIP电容器的下电极。电容器电介质层20和上电极22按顺序形成在掺杂的第一多晶硅层18a上。
如图1D所示，通过用N型材料掺杂第一阱区14a的一个区域可形成集电区28。通过用N型材料掺杂第二阱区14b的一个区域可形成发射区26。通过用P型材料掺杂第二阱区14b的一个区域可形成基区24。基区24和发射区26可彼此隔离。在双极晶体管中，掩埋层12和第一阱区14a与集电区28一起工作。第二阱区14b与基区24一起工作。
biCMOS器件(例如包括CMOS晶体管和双极晶体管的芯片)可包括图1A至图1D所示的结构。与未将CMOS晶体管与双极晶体管集成在一起的器件相比，第一阱区14a中N型材料的浓度相对较低。因此，如果集电区28的串联电阻相对较高，则难以形成具有足够高放大率的双极晶体管。
发明内容
本发明的实施例涉及一种包括双极晶体管和多晶硅/绝缘体/多晶硅(PIP)电容器的biCMOS器件。在本发明的实施例中，biCMOS器件可在双极晶体管处具有相对较低的串联电阻。根据本发明的实施例，双极晶体管可具有理想的放大率。
在本发明的实施例中，biCMOS器件包括半导体衬底、第一阱区、第二阱区、掺杂区和双极晶体管中的至少之一。半导体衬底可为第二导电类型的。第一阱区可掺有第二导电类型材料。第一阱区可形成在半导体衬底的预定区域中。第二阱区可掺有第一导电类型材料。第二阱区与第一阱区相邻。掺杂区可掺有与第一阱区相同的导电类型。掺杂区可形成在第一阱区中。双极晶体管可包括掺有第二导电类型材料的发射区，该发射区位于掺杂区中的半导体衬底表面上。
本发明的实施例涉及一种制造biCMOS器件的方法，包括以下步骤中的至少之一：形成第一阱区、形成场绝缘层、沉积第一多晶硅层、注入离子、除去掩模图案和形成集电区。第一阱区可掺有第二导电类型。第二阱区可掺有第一导电类型。场绝缘层可形成在第一阱区与第二阱区之间的半导体衬底的表面上。第一多晶硅层可形成在场绝缘层上。掩模图案可形成在第一多晶硅层上，用于进行离子注入。通过掩模图案可注入第一导电类型的离子。掺杂区可形成在双极晶体管区的第一阱区中，同时对PIP电容器区的第一多晶硅层进行掺杂。除去用于离子注入的掩模图案。掺有第一导电类型的集电区可形成在掺杂区中的半导体衬底的表面上。
附图说明
图1A至图1D为示出制造biCMOS器件的方法的横截面图。
图2为根据本发明实施例的biCMOS器件的横截面图。
图3A至图3D为示出根据本发明实施例的制造biCMOS器件的方法的横截面图。
具体实施方式
图2为根据本发明实施例的具有PIP电容器和双极晶体管的biCMOS器件的横截面图。图3A至图3D为示出根据本发明实施例制造具有PIP电容器和双极晶体管的biCMOS器件的方法的横截面图。根据本发明的实施例，biCMOS器件可包括双极晶体管和PIP电容器。
如图2所示，双极晶体管包括位于半导体衬底30上的掩埋层32，掩埋层32掺有第二导电类型材料(例如N型材料)。半导体衬底30注入有第一导电类型材料(例如P型材料)。在掩埋层32上方形成外延层(未示出)。
在外延层(未示出)中形成第一阱区34a(例如掺有第二导电类型材料)。靠近第一阱区34a形成第二阱区34b(例如掺有第一导电类型材料)。
在本发明的实施例中，在第一阱区34a中形成掺杂区40。掺杂区40掺有第二导电类型材料。在形成掺杂区40的半导体衬底的表面上形成双极晶体管的集电区46。在本发明的实施例中，通过掺杂区40可减小集电区46的串联电阻。因此，在本发明的实施例中，通过使用掺杂区40能够实现具有相对较高放大率的双极晶体管。
在第二阱区34b中的半导体衬底的表面上形成发射区48(例如掺有第二导电类型材料)。在第二阱区34b中形成基区49(例如掺有第一导电类型材料)。基区49与发射区48分离。在第一阱区34a与第二阱区34b之间的半导体衬底的表面上形成场绝缘层36。
如图2所示，PIP电容器包括形成在半导体衬底30上方的场绝缘层36。在场绝缘层36上方按顺序形成下电极38a(例如掺有第二导电类型材料)、电介质层42和上电极44。
如图3A所示，根据本发明的实施例，半导体衬底30可注入有第一导电类型材料(例如P型材料)。半导体衬底30包括区域A中的PIP电容器和区域B中的双极晶体管。掩埋层32可掺有第二导电类型材料(例如N型材料)。掩埋层32形成在双极晶体管区B中。在掩埋层32上方形成外延层(未示出)。第一阱区34a掺有第二导电类型材料。第二阱区34b掺有第一导电类型材料。第一阱区34a和第二阱区34b彼此相邻并形成在外延层(未示出)中。在半导体衬底30上方形成场绝缘层36。
在场绝缘层36上方形成第一多晶硅层38。在第一多晶硅层38上方形成光致抗蚀剂层(未示出)。执行曝光和显影处理以形成掩模图案39。掩模图案39用于进行离子注入。
为暴露第一阱区34a的预定部分(例如将形成双极晶体管的集电区的区域D)形成掩模图案39。形成掩模图案以暴露第一多晶硅层的区域C。为了暴露第一阱区34a的区域D，要除去掩模图案39下方的第一多晶硅层38。
如图3B所示，执行使用掩模图案39的离子注入工艺。第一阱区34a可被掺杂以形成掺杂区40。第一多晶硅层38可被掺杂以形成掺杂第一多晶硅层38a。掺杂第一多晶硅层38a和掺杂区40可被同时掺杂。
如图3C所示，除去掩模图案39。在掺杂第一多晶硅层38a上执行光致抗蚀剂层的涂布、曝光和显影处理以形成停止蚀刻的掩模图案(未示出)。使用停止蚀刻的掩模图案(未示出)执行蚀刻处理。除去第一多晶硅层38的未掺杂区域，而仅保留掺杂第一多晶硅层38a。掺杂第一多晶硅层38a成为PIP电容器的下电极。然后，除去停止蚀刻的掩模图案(未示出)。电介质层和第二多晶硅层按顺序形成在掺杂第一多晶硅层38a上方并进行图案化以形成电容器电介质层42和上电极44。
如图3D所示，在第一阱区34a的掺杂区40中形成掺有第二导电类型材料(例如N型材料)的集电区46。发射区48掺有第二导电类型材料(例如N型材料)。基区49掺有第一导电类型材料(例如P型材料)。在第二阱区34b中发射区48与基区49相隔离。
在本发明的实施例中，在第一阱区34a中形成掺杂区40以增加第一阱区34a中的第二导电类型材料的浓度。根据本发明的实施例，在双极晶体管的运行过程中掺杂区40能够与集电区46一起工作。在本发明的实施例中，由于集电区中的串联电阻相对较低，因此双极晶体管具有高的放大率。
P型材料可以是第一导电类型材料或第二导电类型材料。N型材料可以是第二导电类型材料或第二导电类型材料。
显然，对本领域的技术人员来说能够对本发明的实施例进行各种修改和改变。因此，本发明涵盖落入所附权利要求范围内的对本发明实施例的修改和改变。

Claims (18)

1.一种装置，包括：
半导体衬底；
第一阱区，掺有第二导电类型材料并形成在该半导体衬底的第一区中；
第二阱区，掺有第一导电类型材料并形成在该半导体衬底的第二区中，其中该第二阱区与该第一阱区相邻；
第一阱区的掺杂区，掺有该第二导电类型材料；
集电区，形成在该掺杂区中；以及
发射区，形成在该第二阱区中。
2.根据权利要求1所述的装置，其中该装置为双极晶体管。
3.根据权利要求2所述的装置，其中该装置包含于biCMOS器件中。
4.根据权利要求1所述的装置，其中该掺杂区掺杂的该第二导电类型材料的浓度大于该第一阱区的该第二导电类型材料的浓度。
5.根据权利要求1所述的装置，其中该集电区是通过用该第二导电类型材料掺杂该掺杂区的一部分而形成的。
6.根据权利要求1所述的装置，其中该发射区是通过用该第二导电类型材料掺杂该第二阱区的一部分而形成的。
7.根据权利要求1所述的装置，还包括形成在该第二阱区中的基区，其中：
该基区是通过用该第一导电类型材料掺杂该第二阱区的一个区域而形成的；以及
该基区与该发射区相隔离。
8.根据权利要求1所述的装置，还包括形成在该第一阱区和该第二阱区下方的掩埋层。
9.根据权利要求1所述的装置，还包括形成在该第一阱区和该第二阱区的结的上方的场绝缘层。
10.根据权利要求1所述的装置，还包括多晶硅/绝缘体/多晶硅电容器，其中：
在该半导体衬底上方形成场绝缘层；以及
在该场绝缘层上方形成下电极、电容器电介质层和上电极。
11.根据权利要求1所述的装置，其中：
该第一导电类型材料为P型材料；以及
该第二导电类型材料为N型材料。
12.一种方法，包括：
在半导体衬底中形成掺有第二导电类型材料的第一阱区和掺有第一导电类型材料的第二阱区；
在该第一阱区和该第二阱区的结处的半导体衬底上方形成场绝缘层；
在该场绝缘层上沉积第一多晶硅层；
在该第一多晶硅层上方形成掩模图案；
通过该掩模图案注入该第二导电类型材料的离子，以在该第一阱区中形成掺杂区；
通过该掩模图案注入该第二导电类型材料的离子，以掺杂电容器区中的该第一多晶硅层；
除去该掩模图案；以及
在该掺杂区中形成掺有第二导电类型材料的集电区。
13.根据权利要求12所述的方法，其中该电容器区包括多晶硅/绝缘体/多晶硅电容器。
14.根据权利要求12所述的方法，其中该第一阱区和该第二阱区包含于双极晶体管中。
15.根据权利要求12所述的方法，还包括：
在所述的通过该掩模图案注入离子之后，图案化该第一阱区以暴露该第一多晶硅层；以及
在该第一多晶硅层上方形成电容器电介质层和上电极。
16.根据权利要求12所述的方法，还包括：
在该第二阱区中形成具有第二导电类型材料的发射区；以及
在该第二阱区中形成具有第一导电类型材料的基区，其中该基区与该发射区相隔离。
17.根据权利要求12所述的方法，其中该第一导电类型材料为P型材料；以及该第二导电类型材料为N型材料。
18.根据权利要求12所述的方法，还包括：在所述的形成该第一阱区和该第二阱区之前在该半导体衬底中形成掩埋层。
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