CN1941406A - 形成自对准晶体管的方法及其结构 - Google Patents

形成自对准晶体管的方法及其结构 Download PDF

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CN1941406A
CN1941406A CNA2006101539185A CN200610153918A CN1941406A CN 1941406 A CN1941406 A CN 1941406A CN A2006101539185 A CNA2006101539185 A CN A2006101539185A CN 200610153918 A CN200610153918 A CN 200610153918A CN 1941406 A CN1941406 A CN 1941406A
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戈登·M·格里瓦纳
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Semiconductor Components Industries LLC
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Abstract

本发明涉及一种形成自对准晶体管的方法及其结构。在一种实施方式中，形成晶体管时使用两部分导体，以与晶体管的有源区之一发生电接触。

Description

形成自对准晶体管的方法及其结构
技术领域
本发明总地涉及电子技术，更具体地说，涉及形成半导体器件的方法和结构。
背景技术
以前，半导体行业使用多种方法和结构来形成高性能的双极晶体管。为了获得更高的性能，很重要的一点就是使基极触点的尺寸最小，以减小寄生电容。此外，希望能够使用光刻缩放技术来缩小晶体管的尺寸。以前的形成高性能双极晶体管的方法一般依赖于槽蚀刻(slotetching)技术，这些技术从制造的角度看通常难以控制并且造价比较高。在2005年1月20日公开的、发明人为Freeman等人的美国专利公开号2005/0012180中公开了这样的双极晶体管的一个例子。用来形成高性能双极晶体管的方法蚀刻出穿过电介质的窄槽，并且使用窄槽作为掩模来形成晶体管的其他部分。这些以前的双极晶体管结构还使用多个氧化物或光致抗蚀剂栓来交替地形成发射极开口的外缘和内缘。使用栓来限定开口需要多个工艺步骤，限制了被栓塞的开口的尺寸。
因此，需要一种形成可以在大小尺寸之间容易地缩放的双极晶体管的方法，它不使用槽工艺或者栓技术，并且减少制造成本。
附图说明
图1图示了根据本发明的双极晶体管的放大剖面部分；以及
图2到图7根据形成根据本发明的图1中的晶体管的方法的各个阶段图示了图1中的晶体管的放大剖面部分。
为了图解说明的清楚简明，附图中的元件不一定是按比例绘制的，在不同附图中的相同标记代表相同的元件。此外，为了简化描述，省略了对公知的步骤和元件的描述和详细说明。虽然这里将器件解释为某些N沟道或P沟道器件，但是本领域的普通技术人员将会明白：根据本发明，互补型器件也是可以的。为了绘图清楚，器件结构的掺杂区被图示为一般具有直线边缘和精确的拐角。但是，本领域的技术人员理解：由于掺杂剂的扩散和活化作用，掺杂区的边缘可能不是直线的，拐角也可能不是精确的角度。
具体实施方式
图1图示了双极晶体管10的放大剖面部分。从下文可以看出，使用光刻技术可以将晶体管10缩放成或小或大的尺寸。晶体管10是双极晶体管，它具有形成晶体管10的基极的掺杂区38和掺杂区39以及形成发射极的掺杂区44。导体18和导体连接体34被形成来提供到基极的电连接。
图2根据生产晶体管10的方法的一种实施方式图示了晶体管10在某一制造阶段的放大剖面图。晶体管10被形成在具有上表面12的半导体衬底11上。在优选实施方式中，晶体管10是形成在半导体衬底11上的PNP双极晶体管，所述半导体衬底11包括重掺杂P型体衬底，在它的上面形成轻掺杂P型外延层，或者有可能形成轻掺杂P型槽区(tub)，用于容纳晶体管10。没有示出这些P型元件，因为它们并非在所有的实施方式中都存在。一般地，在衬底11的表面12上靠近晶体管10的外边缘处形成场效氧化物13。在表面12上由场效氧化物13环绕的部分上形成二氧化硅或氧化物层16。氧化物16通常是热氧化物。形成第一保护层17来覆盖氧化物16。在保护层17的一部分上形成导体18，并上覆于氧化物16之上。此后形成另一个保护层10来覆盖导体18。用于保护层17和19的材料是与用于蚀刻导体18的操作相比使蚀刻速度降低的材料。在优选实施方式中，导体18是掺杂多晶硅，以形成良好的电导体，层17和19是氮化硅。在层19的至少一部分上形成层间电介质20，例如二氧化硅或氧化物，并优选地上覆于全部导体18之上。从下文将会看出，氧化物16、层17和19、导体18和电介质20的厚度都可以影响晶体管10的某些元件的尺寸。
图3根据生产晶体管10的方法的一种实施方式图示了晶体管10在形成电介质20后的一个后续制造阶段的放大剖面部分。向电介质20涂敷掩模23，并使其图案化，以形成上覆于表面12中将形成晶体管10的基极和发射极的部分之上的开口。电介质20的暴露部分以及层19的下伏部分被除去，形成开口24，穿过该开口24将形成晶体管10的有源(active)部分及与它们相连的电触点。用来刻穿电介质20的操作也除去了层19在开口24内的部分。一般地，反应离子蚀刻(RIE)被用来除去电介质20和层19的所述部分。在优选实施方式中，导体18的多晶硅是该操作的蚀刻阻挡。
图4根据生产晶体管10的方法的一种实施方式图示了在后续阶段的晶体管10。导体18暴露在开口24内的部分被除去。在优选实施方式中，用于除去导体18的掺杂多晶硅的暴露部分的工艺在导体18和层17的氮化硅之间是有选择性的，因而，层17形成了该操作的蚀刻停止层。此后如虚线所示，除去掩模23。开口24使电介质20的侧壁、导体18的侧壁以及层19和17的侧壁暴露出来。沿着电介质20、导体18以及层19和17的这些侧壁形成多晶硅隔离体26。隔离体26一般是通过多晶硅的共形均厚沉积来形成的，多晶硅沿着电介质20的顶部，在开口24内沿着电介质20、导体18以及层19和17的侧壁，并且在层17的暴露表面上沉积。此后利用各向异性蚀刻除去多晶硅，留下多晶硅的一部分作为隔离体26。
图5根据生产晶体管10的方法的一种实施方式图示了在后续阶段的晶体管10。隔离体10被氧化，在原来形成隔离体26的地方形成保护隔离体28。一般地，利用湿法氧化将隔离体26形成为隔离体28。隔离体26(图4)和隔离体28的宽度很小，以不妨碍后面形成晶体管10的基极和发射极。在优选实施方式中，隔离体26向开口24内延伸大约50纳米，最终的隔离体28向开口24内延伸大约65纳米。此后，从开口24内以及下伏于导体18之下的第一距离31内除去层17。在除去层17后，从与层17大约相同的区域内除去层16的暴露部分。保护隔离体28在这些操作期间保护电介质20、导体18和层19的侧壁。除去层17和16的操作在导体18的下方向内切除，形成了下伏于导体18之下的凹口29，它暴露出导体18的具有下表面30的一个悬凸部分(ledge)。在优选实施方式中，通过在磷酸中进行湿法氮化物蚀刻约60分钟来除去层17的所述部分，用以形成约10纳米的距离31。在该优选实施方式中，利用蚀刻氧化物的基于HF的湿法蚀刻来除去氧化物16的所述部分，而该蚀刻方法对于层17和导体18是有选择性的。除去层16的操作也从隔离体28中除去了类似的量，使隔离体28变薄，但是使侧壁相对于表面12基本上还保持垂直。从下文将会看到，距离31是很重要的，有助于使晶体管10的非本征或者非有源(inactive)基极的宽度最小。
图6根据生产晶体管10的方法的一种实施方式图示了接下来的阶段。在凹口29中形成导体连接体34，它被用来将导体18互连到接下来将被形成为掺杂区38的非有源基极。连接体34一般是通过沿着表面12在开口24内被暴露的部分，在电介质20、隔离体28上，向凹口29内施加掺杂多晶硅的共形层而形成的。共形多晶硅被沉积到不小于凹口29的深度的一半的厚度。用各向异性蚀刻来除去多晶硅，但留下多晶硅的一部分作为连接体34，该部分填充凹口29并且下伏于导体18和隔离体28之下。优选地，多晶硅共形层被形成到大约50纳米的厚度。此后，穿过开口24使晶体管10被氧化，从而沿着隔离体28的侧壁、连接体34的侧壁和表面12的暴露部分形成二氧化硅层或氧化物层35。优选地，氧化物层35被形成为约70纳米的厚度。在优选实施方式中，使用热氧化循环，热氧化循环也将掺杂剂从导体18驱动到连接体34和衬底11内，以形成晶体管10的基极的非本征部分作为第一表面12上的掺杂区38。这确保了在连接体34和区38之间实现电阻非常低的电连接。
通过穿过开口24掺杂表面12的一部分来在表面12上形成掺杂区39，从而形成了器件的有源基区。优选地，区39是通过将掺杂剂穿过氧化物层35注入到衬底11中而形成的。在优选实施方式中，使用能量为30KeV的约2.5E13的硼离子注入。
图7根据生产晶体管10的方法的一种实施方式图示了另一个后续的阶段。在优选实施方式中，在开口24内沉积约300纳米的不掺杂多晶硅，接着进行各向异性蚀刻，使多晶硅填充物41沿着层35的侧壁保留下来，沿着层35的底部的一部分延伸。此后，比如通过湿法氧化物蚀刻或者反应离子蚀刻，除去层35中沿着层35的底部的暴露部分，留下层35的剩余部分作为对准隔离体36。
再次参考图1，在表面12中被隔离体36和填充物41暴露出的部分上形成掺杂区44作为发射极。掺杂区44也是浅的，向区39内扩展一段短距离。为了形成区44，用导体43填充开口24的剩余部分，该导体43也将是用于形成区44的掺杂剂源。导体43一般用与区39的掺杂类型相反的掺杂类型来掺杂。在优选实施方式中，导体43是用磷掺杂的多晶硅。使用导体43作为掺杂剂源有助于控制区44的深度。在该优选实施方式中，利用快速热退火将掺杂剂从对区44进行掺杂的导体43中驱动到不大于层39的深度的深度中。注意，导体43形成与区44电接触，从而与晶体管10的发射极电接触的发射极电极。导体18和连接体34形成基极电极，该电极提供到由区38和39形成的晶体管10的基极的电接触。可以看出，隔离体28、36和填充物41的宽度是很重要的，它们决定了晶体管10的有源区的尺寸。隔离体36的宽度决定了有源基区的宽度，还决定了晶体管10的发射极的宽度。还可以看出，用于形成隔离体的步骤是可缩放的，可被用来形成具有更小或更大有源区的晶体管。此外，用于形成隔离体28和36以及填充物41的方法形成了基本上竖直或者垂直于表面12的侧壁，这有助于准确地定位有源元件，以及准确地确定晶体管10的有源元件的间隔和尺寸。目标是使侧壁完全垂直于表面12。然而，本领域的技术人员知道，在工艺和温度上可能存在微小的偏差，使侧壁不能完全垂直于表面12。本领域公认的是：多达约15度的偏差都被视为与完全垂直于表面12的理想目标之间的合理偏差。
基于以上描述很清楚的是：已公开了一种新颖的器件和方法。其中，除了一些其他特征之外，包括以下特征：在导体下方形成凹口，用导电材料填充该凹口，以电接触晶体管的基区。使用两个不同的导体有助于形成具有基本竖直的侧壁，使得所述侧壁基本上垂直于衬底表面的对准隔离体。对准隔离体的得到改进的侧壁改善了有源区之间的对准，有助于形成更小的有源区，使得所述方法和器件可被缩放为更大或更小的尺寸。
虽然结合具体的优选实施方式描述了本发明的主题，但是很明显：很多替换和变体方案对于半导体领域的技术人员而言都将是显然的。例如，隔离体28是可选的，在一些实施方式中可以省略。此外，填充物41可以是任意数量的材料，导电的或非导电的，区44可以被注入或扩散，区38和39可以是一个注入层，连接体34可以是其他导电材料。此外，在形成了发射极开口后可以除去填充物41，或者填充物41可以被省略，表面12的发射区可以由光刻工艺形成。虽然形成区44和39的方法被图示为分别形成晶体管10的发射极和基极，但是对于其他晶体管结构而言，每个区的功能和掺杂情况都可以根据器件要求而变。另外，晶体管的多个部分可以形成在场效氧化物层的顶上。更具体地，本说明书针对一种特定的NPN晶体管结构描述了本发明的主题，但是该方法可直接应用于PNP双极晶体管、二极管，也可以应用于MOS、BiCMOS、金属半导体FET(MESFET)、HFET以及其他晶体管结构。本领域的普通技术人员将会明白：所图示的步骤仅仅是示例性的，仅构成了在半导体衬底11上形成晶体管10所需的制造工艺步骤的一部分。

Claims (10)

1.一种用于晶体管的接触结构，包括：
具有第一表面的半导体衬底；
第一表面上的第一掺杂区；
位于第一表面上，与第一掺杂区电接触的第二掺杂区；
上覆于第一掺杂区之上的具有第二表面的第一导体，该第一导体具有侧壁；以及
下伏于第一导体的一部分之下，从第二表面延伸以与第一掺杂区电接触的第二导体，其中，第二导体不在第一导体的侧壁上。
2.如权利要求1所述的接触结构，还包括在第一导体的侧壁上的保护隔离体。
3.如权利要求1所述的接触结构，还包括基本上与第一导体的侧壁共面的对准隔离体，其中，第一导体的侧壁基本上垂直于第一表面。
4.如权利要求3所述的接触结构，其中，所述对准隔离体具有上覆于第二掺杂区之上的开口。
5.如权利要求3所述的接触结构，其中，所述对准隔离体位于所述第一导体和第三导体之间。
6.一种形成晶体管的方法，包括：
提供具有第一表面的半导体衬底；
形成具有第二表面的第一导体，该第一导体上覆于第一表面的第一部分之上，并具有侧壁；
形成第二导体，该第二导体从第二表面延伸，以与第一表面的第一部分电接触，其中，第二导体不在第一导体的侧壁上；
在第一表面中，下伏于第二导体之下形成第一掺杂区；
在第一表面的第二部分上形成第二掺杂区；
形成第三导体，该第三导体上覆于第二掺杂区之上，并且与第二掺杂区电接触。
7.如权利要求6所述的方法，其中，形成从第二表面延伸的第二导体的步骤包括：形成穿过第一导体、暴露出第一导体的侧壁的开口，在第一导体的侧壁上形成保护隔离体，形成下伏于第一导体之下的凹口，以及用导电材料填充所述凹口。
8.如权利要求7所述的方法，还包括：在形成第二导体之前形成上覆于第一导体之上的电介质，形成穿过所述电介质，暴露出所述电介质的侧壁和第一导体的侧壁的所述开口，以及在所述电介质的侧壁和第一导体的侧壁上形成所述保护隔离体。
9.一种形成半导体器件的方法，包括：
提供具有第一表面的半导体衬底；
形成具有第二表面的第一导体，该第一导体上覆于第一表面的第一部分之上并具有侧壁；
形成第二导体，该第二导体位于第二表面上，与所述半导体衬底的第一表面的第一部分上的第一掺杂区电接触，该步骤包括形成从第二表面的一部分延伸，并且不在第一导体的侧壁上的第二导体；
形成位于第一表面的第二部分上，与第一掺杂区电接触的第二掺杂区；以及
形成第三导体，该第三导体上覆于第二掺杂区之上，与第二掺杂区电接触，但不接触第一导体或第二导体。
10.如权利要求9所述的方法，其中，形成位于第二表面上，与第一掺杂区电接触的第二导体的步骤包括：在第二表面上形成第二导体之前，在第一导体的侧壁上形成保护隔离体。
CN2006101539185A 2005-09-30 2006-09-12 形成自对准晶体管的方法及其结构 Expired - Fee Related CN1941406B (zh)

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