CN1954427A - 功率半导体组件 - Google Patents
功率半导体组件 Download PDFInfo
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- CN1954427A CN1954427A CNA2005800151532A CN200580015153A CN1954427A CN 1954427 A CN1954427 A CN 1954427A CN A2005800151532 A CNA2005800151532 A CN A2005800151532A CN 200580015153 A CN200580015153 A CN 200580015153A CN 1954427 A CN1954427 A CN 1954427A
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Abstract
一种功率半导体组件(1,30,40),具有第一有源半导体部件(2)和第二有源半导体部件(3),它们的电接线(8,14)以连接腿(9,15)的形式引出半导体部件。第一半导体部件(2)通过插入式连接至少部分地电连接到第二半导体部件(3)。该插入式连接借助于将第二半导体部件(3)的连接腿(15)啮合到第一半导体部件的电接线(8)内实现。
Description
本发明涉及专利权利要求1的前序部分中所述的功率半导体装置。
制作功率半导体装置时,为节省成本,努力实现最高可能集成度。这样做的缺点在于高的集成度使得更难将功率半导体装置的各个部件进行接触连接。
提高集成度有很多方法:文件DE 101 34 986 A1讲授了适配器模块的使用。文件DE 199 23 523 A1和DE 101 23 869 A1证明了提高电子装置自身集成度的可能性。而且,DE 198 33 713 C1公开了使用特定的连接技术将一个电子部件安置在另一部件之上的实践。DE 19933 265 A1描述了使用合成体将电子部件安置在另一部件之上的实践。
本发明的目的是在功率半导体装置中实现高集成度,同时以可靠的方式接触连接功率半导体装置的部件。
为了获得该目的,本发明提供了专利权利要求1所述的功率半导体装置。可以在从属权利要求中找到本发明的概念的有利改善和发展。
该功率半导体装置具有第一有源半导体部件和第二有源半导体部件。每个半导体部件都具有以连接腿的形式延伸出半导体部件的电接线。通过插入式连接,第一半导体部件至少部分地与第二半导体部件电连接。插入式连接借助于将第二半导体部件的连接腿啮合到第一半导体部件的电接线中实现。
术语“有源半导体部件”,具体而言理解成诸如晶体管之类的控制部件,也可以理解成集成电路或芯片。优选地,有源半导体部件代表功率半导体部件。
第二半导体部件的连接腿优选地啮合到第一半导体部件的连接腿中。为此,一个优选实施例中,第二半导体部件的连接腿(至少一个连接腿)分别具有凹槽,且第一半导体部件的连接腿(至少一个连接腿)分别具有孔。凹槽和孔的尺寸以这样的方式相互匹配:当第二半导体部件的连接腿插入第一半导体部件的连接腿的相应孔中时,连接腿互锁。这样可以实现同样可靠和大规模的集成接触连接。
第二半导体部件可以例如,安置在第一半导体部件上面,也可以安置在第一半导体部件的旁边。
本发明并不局限于仅具有两个有源半导体部件的功率半导体装置。而是,有源半导体部件的数目可以是任意的。例如,如果第二半导体部件安置在第一半导体部件上,另外的半导体部件可以安置在第二半导体部件上,所述另外的部件的每个连接腿都啮合到其下的半导体部件的连接腿中。这样可以实现包括有源半导体部件的任意所需复合层结构。
根据本发明的功率半导体装置可以具有无源部件,其电接线或连接腿通过插入式连接与有源半导体部件的电接线或连接腿电连接。换句话说:本发明的插入式连接的原理还可以应用于这样的功率半导体装置,它除了具有有源半导体部件,还具有无源部件,例如电容器或电阻器。这样可以构建具有任意所需数目的有源和无源部件的功率半导体装置,这些部件通过插入式连接彼此电连接。
已经指出,原则上,插入式连接可以位于有源半导体部件之一内部或位于无源部件之一内部和/或位于有源半导体部件或无源部件的外部。
有源半导体部件或无源部件的电接线和/或连接腿可以以这样的方式构建:通过插入式连接形成电学接触,所述电接触是弹性接触、挤压接触,夹钳接触等。例如,依靠连接腿的环形形状,连接腿可以在电接线/连接腿上施加横向力,这样,当连接腿插入其它连接腿或电接线时可以形成挤压/夹钳接触。
因此,根据本发明的功率半导体装置可以减小印刷电路板和基片上导电迹线的数目。而且,减小了由导线引起的损耗和干扰。本发明的基本方案是将电子装置的已有部件用于插入式连接或用作重新布线平面。这样可以布置额外的模块和导电迹线。
下面,将参考附图,在示例性实施例中详细描述本发明:
图1示出了根据本发明的功率半导体装置的第一实施例的横截面示意图,
图2示出了图1所示的插入式连接的一个优选实施例,
图3示出了根据本发明的功率半导体装置的应用实例的示意图,
图4示出了图3所示的功率半导体装置的一个可能的连接图,
图5示出了根据本发明的功率半导体装置的第二实施例的横截面示意图,
图6示出了根据本发明的功率半导体装置的第三实施例的横截面示意图,
图7示出了根据现有技术的第一功率半导体装置,
图8示出了根据现有技术的第二功率半导体装置。
图中,相同或相互对应的装置或装置组使用相同的参考符号标记。
图1所示的第一实施例1具有第一有源半导体部件2和第二有源半导体部件3,该第二有源半导体部件3位于第一有源半导体部件2上。
第一有源半导体部件2具有外壳4,其中在载体元件6上提供半导体部件5。半导体部件5通过接触元件7接触连接,该接触元件7又与电接线8相连。电接线8以连接腿9的形式延伸出外壳5。
与此类似,第二有源半导体部件3具有外壳10,其中安置有载体元件11和位于载体元件之上的半导体部件12。半导体部件12通过接触元件13接触连接,接触元件13又与电接线14连接。电接线14以连接腿15的形式延伸出外壳10,并通过相应的孔插入到第一有源半导体部件2的外壳4内,并且嵌入到电接线8中,结果是,在连接腿15和电接线8的端部之间产生电学连接。这样第一有源半导体部件2的装置元件(电接线8)用于接触连接第二有源半导体部件3。这样,一方面可以增加集成度,另一方面,减小了导线引入的损耗和干扰。
连接腿15的端部嵌入到电接线14内的连接部分以插入式连接的形式实现,在图2中可以发现这种插入式连接的一个优选实施例。该实施例中,每个电接线8具有孔16,连接腿15的端部可以穿过该孔。而且,可以在连接腿15的端部提供凹槽17,它可以与孔16的轮廓相啮合并由此在有源半导体部件2、3之间提供稳定的插入式连接。
一个优选实施例中,第二有源半导体部件3是控制芯片(IC)且第一有源半导体部件2是功率半导体部件,例如功率晶体管。
图3中,第一到第三有源半导体部件2、3和17彼此相连以形成功率半导体装置22(桥电路)。本发明可以以两种方式应用于半导体装置22:
一方面,延伸出第二有源半导体部件3的连接腿18可以基于插入式连接与延伸出第一有源半导体部件2的连接腿19电连接;与此类似,延伸出第三有源半导体部件17的连接腿20可以基于插入式连接与延伸出第一有源半导体部件2的连接腿21电连接。本发明的插入式连接可以以同样简单、可靠和大规模集成的方式将半导体部件2、3和17连接在一起。例如,图3所示的功率半导体装置用于连接电机或开关式电源,各个部件可以通过单独的IC或多个IC控制和调整。
另一方面,通过插入式连接,可以将其它半导体部件插入到半导体装置22上。使用图4举例证明这点。
图4示出了图3所示的功率半导体装置的一种可能的连接图。该实施例中,接触区域24中的一些不需要接触连接半导体装置22,例如用参考符号25标记的接触区域。根据本发明,因此接触区域25可以用于接触连接设置在所述接触区域之上的有源半导体部件(例如控制芯片或其它半导体功率部件)(此处未示出)。例如,可以在接触区域25中提供孔,安置在上面的有源半导体部件的连接腿可以通过所述孔插入,以形成与接触区域25的电学连接。这样可以使用功率半导体装置22的导电迹线(它们已经存在,但并不需要与该功率半导体装置接触连接),并由此节省空间、增加集成密度以及获得电学性能的提高。
图5示出了根据本发明的功率半导体装置的第二实施例30。该实施例中,第一、第二和第三有源半导体部件2、3和17彼此堆叠,第三有源半导体部件17的连接腿31以插入式连接的形式,啮合到第二有源半导体部件3的连接腿32中。而且,第二有源半导体部件3的连接腿32以插入式连接的形式啮合到第一有源半导体部件2的连接腿33中。因为上面的有源半导体部件的连接腿每个都啮合到其下的半导体部件的连接腿中,这样仅连接腿33需要焊接到印刷电路板34上。
因为连接腿31、32具有环形形式,当连接腿31啮合到连接腿32中时,连接腿31有可能向连接腿32施加横向力。类似地,对于连接腿32啮合到连接腿33中,情况相同。这样可以在连接腿31、32和33之间以简单的形式获得稳定的电学夹钳接触。一般而言,连接腿之间的电学接触的质量可以通过连接腿31~33的特定几何形状优化。
图6所示的第三实施例40示出了第一、第二和第三有源半导体部件2、3和17,第一和第二有源半导体部件2、3彼此并排安置,并且第三有源半导体部件17借助于啮合到第一有源半导体部件2的连接腿33中的第三有源半导体部件17的连接腿31,以及啮合到第二有源半导体部件3的连接腿32中的第三有源半导体部件17的另一连接腿31,连接这两个半导体部件2、3。例如,第三有源半导体部件17是控制芯片,第一和第二有源半导体部件2、3可以是功率部件,例如,晶体管。然而,本发明不受此限制。
图7示出了根据现有技术的有源半导体部件50,孔52制作在所述部件的外壳(模制成分和引线框)51中。在安装半导体部件50时需要这些孔,即它们总是存在,且根据本发明,可用于将半导体部件(此处未示出)的连接腿(该半导体部件位于所述连接腿上)插入到半导体部件50的外壳51中。这样,穿过孔52的电接线(此处未示出)可以与上述半导体部件的连接腿(该半导体部件位于所述连接腿上)相接触。因此,在该特定情况下,没有必要为了实现如图1所示的插入式连接而制作额外的孔。根据本发明,当使用外壳51时,孔52还可以设置在模制成分的其它区域中和引线框的其它区域中,或连接腿的其它区域中。
图8示出了根据现有技术的功率半导体装置。该实施例中,在印刷电路板53上提供第一、第二和第三有源半导体部件2、3、17。这种情况下,在第一有源半导体部件2上提供第三有源半导体部件17,且第二有源半导体部件3安置在第一有源半导体部件2的旁边。该实施例中,第一和第二有源半导体部件2、3是功率半导体部件且第三有源半导体部件17是控制芯片。半导体部件17通过电接线54与第一和第二有源半导体部件2、3连接,以及与印刷电路板53的接触区域55相连接。而且,第一有源半导体部件2通过电接线56与接触区域55相连,第二有源半导体部件3通过电接线57与接触区域55相连。
可以清楚地看出,有源半导体部件2、3和17的设计规则必须彼此极其匹配,这具有这样缺点,不能充分地使用印刷电路板53上的可用空间。此外,该实施例中,有源半导体部件2、3不能被不同的控制芯片驱动,因为,考虑到第二有源半导体部件3的小的尺寸,尤其是,任何半导体部件,例如控制芯片,不能在有源半导体部件2、3上找到空间。根据本发明的功率半导体装置避免了这些缺点。根据本发明,因为使用了现有装置元件,控制芯片17的几何结构很大程度上独立于半导体部件2、3的几何结构,因此即使比下面的半导体部件大,半导体部件仍可以堆叠在下面的半导体部件上。
参考符号列表:
1 第一实施例
2 第一有源半导体部件
3 第二有源半导体部件
4 外壳
5 半导体元件
6 载体元件
7 接触元件
8 电接线
9 连接腿
10 外壳
11 载体元件
12 半导体部件
13 接触元件
14 电接线
15 连接腿
16 孔
17 第三有源半导体部件
17a 凹槽
18-21 连接腿
22 功率半导体部件
23 半导体元件
24,25 接触元件
30 第二实施例
31-33 连接腿
34 印刷电路板
40 第三实施例
50 有源半导体部件
51 外壳
52 孔
53 印刷电路板
54 电接线
55 接触区域
56,67 电接线
Claims (9)
1.一种功率半导体装置(1,30,40),具有第一(2)有源半导体部件和第二(3)有源半导体部件,它们的电接线(8,14)以连接腿(9,15)的形式延伸出所述半导体部件,第一半导体部件(2)通过插入式连接至少部分地电连接到第二半导体部件(3),
其中借助于将第二半导体部件(3)的连接腿(15)啮合到第一半导体部件的电接线(8)中提供所述插入式连接。
2.权利要求1所述的功率半导体装置(30,40),其中第二半导体部件(3)的连接腿(32)啮合到第一半导体部件(2)的连接腿(33)中。
3.权利要求1或2所述的功率半导体装置(1,30,40),其中
第二半导体部件的至少一个连接腿(15)具有凹槽(17a),且第一半导体部件的至少一个连接腿(8)具有孔(16),凹槽的尺寸和孔的尺寸以这样的方式相互匹配:当第二半导体部件的连接腿插入到第一半导体部件的连接腿中的孔中时,所述连接腿互锁。
4.权利要求1到3之一所述的功率半导体装置(1,30),其中第二半导体部件位于第一半导体部件之上。
5.权利要求4所述的功率半导体装置(30),其中另外的半导体部件(17)安置在第二半导体部件(32)之上,这些部件的连接腿(31,32)每一个都啮合到它们下面的半导体部件的连接腿(32,33)中。
6.权利要求1到3之一所述的功率半导体装置(40),其中第二半导体部件(3)安置在第一半导体部件(2)旁边。
7.前述权利要求之一所述的功率半导体装置(1,30,40),其中该功率半导体装置具有无源部件,无源部件的电接线或连接腿通过插入式连接与有源半导体部件(2,3)的电接线或连接腿电连接。
8.前述权利要求之一所述的功率半导体装置(1,30,40),其中插入式连接位于有源半导体部件(2,3)之一内部或位于无源部件之一内部和/或位于有源半导体部件或无源部件外部。
9.前述权利要求之一所述的功率半导体装置(1,30,40),其中有源半导体部件(2,3)的或无源部件的电接线和/或连接腿以这样的方式配置:通过插入式连接形成电接触,所述电接触是弹性接触、挤压接触、夹钳接触等。
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Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56116650A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor device |
CH664250A5 (de) * | 1984-04-02 | 1988-02-15 | Sprecher & Schuh Ag | Steckbares gehaeuse zur auswechselbaren aufnahme eines integrierten schaltungsbausteines. |
JPS61108154A (ja) * | 1984-11-01 | 1986-05-26 | Nec Corp | 集積回路ケ−ス実装方式 |
JPH02271655A (ja) | 1989-04-13 | 1990-11-06 | Hitachi Ltd | 半導体装置およびモジュール |
JPH053082A (ja) | 1991-06-24 | 1993-01-08 | Hitachi Maxell Ltd | エレクトロルミネツセント素子および光感応装置 |
JP3293334B2 (ja) | 1993-08-25 | 2002-06-17 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
JPH0794674A (ja) | 1993-09-20 | 1995-04-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6277225B1 (en) * | 1996-03-13 | 2001-08-21 | Micron Technology, Inc. | Stress reduction feature for LOC lead frame |
JPH1012811A (ja) * | 1996-06-21 | 1998-01-16 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
DE19833713C1 (de) * | 1998-07-27 | 2000-05-04 | Siemens Ag | Verfahren zur Herstellung eines Verbundkörpers aus wenigstens zwei integrierten Schaltungen |
DE19923523B4 (de) * | 1999-05-21 | 2004-09-30 | Infineon Technologies Ag | Halbleitermodul mit übereinander angeordneten, untereinander verbundenen Halbleiterchips |
DE19933265A1 (de) * | 1999-07-15 | 2001-02-01 | Siemens Ag | TSOP-Speicherchipgehäuseanordnung |
JP3798620B2 (ja) * | 2000-12-04 | 2006-07-19 | 富士通株式会社 | 半導体装置の製造方法 |
DE10134986B4 (de) * | 2001-07-18 | 2004-04-29 | Infineon Technologies Ag | Verbindung gehäusegefaßter integrierter Speicherbausteine mit einer Leiterplatte |
JP2003347509A (ja) * | 2002-05-28 | 2003-12-05 | Omron Corp | 高熱伝導性樹脂封止電子回路基板とその製造方法 |
-
2004
- 2004-05-11 DE DE102004023307A patent/DE102004023307B3/de not_active Expired - Fee Related
-
2005
- 2005-05-04 JP JP2007511853A patent/JP4444335B2/ja not_active Expired - Fee Related
- 2005-05-04 CN CNB2005800151532A patent/CN100557799C/zh not_active Expired - Fee Related
- 2005-05-04 WO PCT/DE2005/000848 patent/WO2005112117A2/de active Application Filing
- 2005-05-04 US US11/568,885 patent/US8299585B2/en active Active
Also Published As
Publication number | Publication date |
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US20090045446A1 (en) | 2009-02-19 |
DE102004023307B3 (de) | 2005-10-20 |
US8299585B2 (en) | 2012-10-30 |
WO2005112117A2 (de) | 2005-11-24 |
JP4444335B2 (ja) | 2010-03-31 |
JP2007536749A (ja) | 2007-12-13 |
CN100557799C (zh) | 2009-11-04 |
WO2005112117A3 (de) | 2006-02-02 |
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