CN1953161A - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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Publication number
CN1953161A
CN1953161A CNA2006101361869A CN200610136186A CN1953161A CN 1953161 A CN1953161 A CN 1953161A CN A2006101361869 A CNA2006101361869 A CN A2006101361869A CN 200610136186 A CN200610136186 A CN 200610136186A CN 1953161 A CN1953161 A CN 1953161A
Authority
CN
China
Prior art keywords
dielectric film
grid
floating grid
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101361869A
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English (en)
Chinese (zh)
Inventor
真田和彦
金森宏治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1953161A publication Critical patent/CN1953161A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
CNA2006101361869A 2005-10-18 2006-10-13 半导体存储装置及其制造方法 Pending CN1953161A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005303387A JP2007115773A (ja) 2005-10-18 2005-10-18 半導体記憶装置およびその製造方法
JP2005303387 2005-10-18

Publications (1)

Publication Number Publication Date
CN1953161A true CN1953161A (zh) 2007-04-25

Family

ID=37947366

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101361869A Pending CN1953161A (zh) 2005-10-18 2006-10-13 半导体存储装置及其制造方法

Country Status (3)

Country Link
US (1) US20070085132A1 (enExample)
JP (1) JP2007115773A (enExample)
CN (1) CN1953161A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935586A (zh) * 2015-12-31 2017-07-07 力晶科技股份有限公司 存储器结构

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI281753B (en) * 2005-12-13 2007-05-21 Powerchip Semiconductor Corp Non-volatile memory and manufacturing method and operating method thereof
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9761689B2 (en) * 2014-09-12 2017-09-12 Globalfoundries Inc. Method of forming a semiconductor device and according semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343063A (en) * 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
ATE238609T1 (de) * 1991-08-29 2003-05-15 Hyundai Electronics Ind Selbstjustierende flash-eeprom-zelle mit doppelbit-geteiltem gat
JP3710880B2 (ja) * 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
US6798012B1 (en) * 1999-12-10 2004-09-28 Yueh Yale Ma Dual-bit double-polysilicon source-side injection flash EEPROM cell
JP4027656B2 (ja) * 2001-12-10 2007-12-26 シャープ株式会社 不揮発性半導体記憶装置及びその動作方法
US7443725B2 (en) * 2003-01-22 2008-10-28 Nxp B.V. Floating gate isolation and method of making the same
US6930348B2 (en) * 2003-06-24 2005-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Dual bit split gate flash memory
JP2005051227A (ja) * 2003-07-17 2005-02-24 Nec Electronics Corp 半導体記憶装置
JP2005085903A (ja) * 2003-09-05 2005-03-31 Renesas Technology Corp 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106935586A (zh) * 2015-12-31 2017-07-07 力晶科技股份有限公司 存储器结构

Also Published As

Publication number Publication date
US20070085132A1 (en) 2007-04-19
JP2007115773A (ja) 2007-05-10

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WD01 Invention patent application deemed withdrawn after publication