JP5264139B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5264139B2 JP5264139B2 JP2007263502A JP2007263502A JP5264139B2 JP 5264139 B2 JP5264139 B2 JP 5264139B2 JP 2007263502 A JP2007263502 A JP 2007263502A JP 2007263502 A JP2007263502 A JP 2007263502A JP 5264139 B2 JP5264139 B2 JP 5264139B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000003860 storage Methods 0.000 claims abstract description 36
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 230000001681 protective effect Effects 0.000 claims description 20
- 238000000926 separation method Methods 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 130
- 230000015654 memory Effects 0.000 description 32
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- -1 Silicon Oxide Nitride Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
12 トンネル絶縁膜
14 電荷蓄積層
16 トップ絶縁膜
18 ビットライン
20 ワードライン
22 ゲート絶縁膜
24 ゲート電極
26 OPO膜
28 溝部
30 第2絶縁膜
32 保護膜
34 第1絶縁膜
35 離間領域
36 導電層
38 第1マスク層
39 第1酸化シリコン膜
40 第2マスク層
41 第2酸化シリコン膜
42 第1開口部
45 フォトレジスト
46 第2開口部
48 アンダーカット部
50 層間絶縁膜
52 第3絶縁膜
Claims (13)
- 半導体基板上に第1絶縁膜および導電層を順次形成する工程と、
前記導電層上に、第1方向に延伸する第1マスク層を形成する工程と、
前記第1マスク層間の前記第1方向で離間した領域である離間領域の前記導電層上に第2マスク層を形成する工程と、
前記第1マスク層および前記第2マスク層をマスクに、前記導電層および前記第1絶縁膜を除去して第1開口部を形成する工程と、
前記第1開口部内と前記離間領域の前記導電層上とに第2絶縁膜を形成する工程と、
前記第2絶縁膜をマスクに、前記第1マスク層、前記導電層および前記第1絶縁膜を除去して第2開口部を形成し、前記第2開口部間に前記導電層からなるゲート電極を形成する工程と、
前記第2開口部から前記ゲート電極下に形成された前記第1絶縁膜を除去して、前記ゲート電極の中央下に前記第1絶縁膜からなるゲート絶縁膜を形成する工程と、
前記ゲート電極下に形成された前記第1絶縁膜を除去した領域に電荷蓄積層を形成する工程と、を有する、
半導体装置の製造方法。 - 前記第2絶縁膜を形成する工程は、前記第1開口部に埋め込まれるように、前記第2絶縁膜を形成する工程である、
請求項1記載の半導体装置の製造方法。 - 前記第1開口部の下方の前記半導体基板に溝部を形成する工程を有し、
前記第2絶縁膜を形成する工程は、前記溝部に埋め込まれるように、前記第2絶縁膜を形成する工程を含む、
請求項1または2記載の半導体装置の製造方法。 - 前記半導体基板を酸化させて、前記第1開口部の下方の前記半導体基板表面に第3絶縁膜を形成する工程を有する、
請求項1または2記載の半導体装置の製造方法。 - 前記第2絶縁膜の材料は、前記ゲート電極下に形成された前記第1絶縁膜を除去して前記ゲート絶縁膜を形成する際、前記第1絶縁膜より除去され難い材料である、
請求項1から4のいずれか一項記載の半導体装置の製造方法。 - 前記第2絶縁膜を形成する工程の前に、前記第1開口部の側面に保護膜を形成する工程を有し、
前記保護膜の材料は、前記ゲート電極下に形成された前記第1絶縁膜を除去して前記ゲート絶縁膜を形成する際、前記第1絶縁膜より除去され難い材料である、
請求項1から5のいずれか一項記載の半導体装置の製造方法。 - 前記第1絶縁膜および前記第2絶縁膜は酸化シリコン膜であり、前記保護膜は窒化シリコン膜である、
請求項6記載の半導体装置の製造方法。 - 前記第1開口部を形成する工程の後における前記第1マスク層の膜厚は、前記第2マスク層の膜厚より厚い、
請求項1から7のいずれか一項記載の半導体装置の製造方法。 - 前記ゲート絶縁膜を形成する工程は、等方性エッチングを用いて前記第1絶縁膜を除去することにより、前記ゲート絶縁膜を形成する工程である、
請求項1から8のいずれか一項記載の半導体装置の製造方法。 - 前記半導体基板内を前記第1方向に延伸し、前記第2開口部で規定されるビットラインを形成する工程を有する、
請求項1から9のいずれか一項記載の半導体装置の製造方法。 - 前記ゲート電極上に、前記第1方向に交差する方向である第2方向に延伸するワードラインを形成する工程を有する、
請求項1から10のいずれか一項記載の半導体装置の製造方法。 - 前記電荷蓄積層は、ポリシリコン膜および窒化シリコン膜のいずれか一方からなる、
請求項1から11のいずれか一項記載の半導体装置の製造方法。 - 形成された前記ゲート電極は、前記ゲート電極の少なくとも一方側で前記第2絶縁膜に接触する、
請求項1記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007263502A JP5264139B2 (ja) | 2007-10-09 | 2007-10-09 | 半導体装置の製造方法 |
PCT/US2008/011628 WO2009048601A1 (en) | 2007-10-09 | 2008-10-08 | Method of fabricating a flash memory device having separated charge storage regions |
TW97138838A TWI473204B (zh) | 2007-10-09 | 2008-10-09 | 製造具有淺溝渠隔離之半導體記憶體裝置的方法 |
Applications Claiming Priority (1)
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JP2007263502A JP5264139B2 (ja) | 2007-10-09 | 2007-10-09 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2009094285A JP2009094285A (ja) | 2009-04-30 |
JP5264139B2 true JP5264139B2 (ja) | 2013-08-14 |
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JP2007263502A Expired - Fee Related JP5264139B2 (ja) | 2007-10-09 | 2007-10-09 | 半導体装置の製造方法 |
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JP (1) | JP5264139B2 (ja) |
TW (1) | TWI473204B (ja) |
WO (1) | WO2009048601A1 (ja) |
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JP5290592B2 (ja) * | 2008-02-18 | 2013-09-18 | スパンション エルエルシー | 半導体装置及びその製造方法 |
JP5358121B2 (ja) * | 2008-05-09 | 2013-12-04 | シャープ株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
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JP3233998B2 (ja) * | 1992-08-28 | 2001-12-04 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP3973819B2 (ja) * | 1999-03-08 | 2007-09-12 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
DE10205079B4 (de) * | 2002-02-07 | 2008-01-03 | Infineon Technologies Ag | Verfahren zur Herstellung einer Speicherzelle |
JP2004071877A (ja) * | 2002-08-07 | 2004-03-04 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
JP2004241503A (ja) * | 2003-02-04 | 2004-08-26 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
US7186607B2 (en) * | 2005-02-18 | 2007-03-06 | Infineon Technologies Ag | Charge-trapping memory device and method for production |
JP4238248B2 (ja) * | 2005-11-11 | 2009-03-18 | シャープ株式会社 | 可変抵抗素子を備えた不揮発性半導体記憶装置の製造方法 |
US7521317B2 (en) * | 2006-03-15 | 2009-04-21 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device and structure thereof |
TWI299911B (en) * | 2006-03-22 | 2008-08-11 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
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2007
- 2007-10-09 JP JP2007263502A patent/JP5264139B2/ja not_active Expired - Fee Related
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2008
- 2008-10-08 WO PCT/US2008/011628 patent/WO2009048601A1/en active Application Filing
- 2008-10-09 TW TW97138838A patent/TWI473204B/zh active
Also Published As
Publication number | Publication date |
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WO2009048601A1 (en) | 2009-04-16 |
JP2009094285A (ja) | 2009-04-30 |
TWI473204B (zh) | 2015-02-11 |
TW200926354A (en) | 2009-06-16 |
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