Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42324—Gate electrodes for transistors with a floating gate
  • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/401—Multistep manufacturing processes
  • H01L29/4011—Multistep manufacturing processes for data storage electrodes
  • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
  • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/401—Multistep manufacturing processes
  • H01L29/4011—Multistep manufacturing processes for data storage electrodes
  • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
  • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
  • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

• the present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device including a separated charge storage layer.
• non-volatile memories which are semiconductor devices that can rewrite data and keep storing memory data even when the power is off.
• a flash memory a popular example of a non-volatile memory
• a transistor constituting a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by storing charges in the charge storage layer.
• Flash memories having an insulating film as a charge storage layer includes a flash memory having a silicon oxide nitride oxide silicon (SONOS) structure that stores charges in a charge storage layer in an oxide nitride oxide (ONO) film.
• SONOS silicon oxide nitride oxide silicon
• ONO oxide nitride oxide
• United States Patent No. 6011725 discloses one conventional example of such a SONOS flash memory, a flash memory including a virtual ground memory cell that symmetrically operates a source and a drain by selectively using the source and the drain.
• FIG. 1 is a cross-sectional view of a flash memory according to the cited conventional example of a SONOS flash memory.
• a tunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 are sequentially provided on a semiconductor substrate 10.
• Bit lines 18 that serve as both a source and a drain are provided being extended in the semiconductor substrate 10.
• a gate electrode 24 is provided on the top insulating film 16 between the bit lines 18.
• a distance L between the bit lines 18 is a channel length.
• Japanese Patent Application Publication No. JP-A-2005-108915 and Japanese Patent Application Publication No. JP-A-2004-343014 disclose a technology of forming a gate electrode via a gate insulating film on a semiconductor substrate, removing a part of a side wall of the gate electrode, or both a part of a side wall of the gate electrode and a part of the gate insulating film, forming the charge storage layer in such removed region, and thereby forming a separated charge storage layer.
• CBD complementary bit disturb
• One embodiment of the present invention provides a method for manufacturing a semiconductor device includes: sequentially forming a first insulating film and a conductive layer on a semiconductor substrate; forming a separated first mask layer extending in a first direction on the conductive layer; forming a separated second mask layer on the conductive layer in isolation regions isolated in the first direction so as to interpose in the separated first mask layer; forming first openings by removing the conductive layer and the first insulating film by using the separated first mask layer and the separated second mask layer as a mask; forming a separated second insulating film in the first openings and in the isolation regions on the separated conductive layer; forming second openings by removing the separated first mask layer, the separated conductive layer and the separated first insulating film by using the separated second insulating film as a mask, and thereby forming gate electrodes composed of the separated conductive layer between the second openings; removing, through the second openings, the separated first insulating film formed below the gate electrodes, and thereby forming a separated gate
• the width of the separated second insulating film in the direction crossing the first direction can be made larger than the separated gate insulating film in the direction crossing the first direction.
• the separated second insulating film and the separated gate insulating film can be formed aligned alternately in the first direction.
• tilting of the gate electrodes formed on the separated gate insulating film can be prevented.
• the gate electrodes are formed in a self-aligned manner to the separated second insulating film, tilting of the gate electrodes can be further prevented.
• the charge storage layer can be formed in a separated manner so as to interpose in the separated gate insulating film in the direction crossing the first direction, effects of the CBD can be suppressed.
• forming the separated second insulating film may comprise forming the separated second insulating film so as to be embedded in the first openings. Accordingly, tilting of the gate electrodes can be suppressed.
• the method may also include forming grooves in the semiconductor substrate below the first openings. Forming the separated second insulating film may also include forming the separated second insulating film so as to be embedded in the grooves. In this embodiment, fringe current that flows in the semiconductor substrate in the periphery of the gate electrodes can be suppressed.
• the method may also include forming, a separated third insulating film on a surface of the semiconductor substrate on a lower side of the first openings by oxidizing the semiconductor substrate.
• the fringe current that flows in the semiconductor substrate in the periphery of the gate electrodes can be suppressed.
• a material of the separated second insulating film may be a material that is less likely to be removed than the separated first insulating film during the process of removing the separated first insulating film formed below the gate electrodes to form the separated gate insulating film.
• the width of the separated second insulating film in the direction crossing the first direction can easily be made larger than the width of the separated gate insulating film in the direction crossing the first direction.
• the method may also include forming a separated protective film on side faces of the first openings prior to forming the separated second insulating film.
• a material of the separated protective film may be, when removing the separated first insulating film formed below the gate electrodes to form the separated gate insulating film, a material that is less likely to be removed than the separated first insulating film.
• the width of the separated second insulating film in the direction crossing the first direction can easily be made larger than the width of the separated gate insulating film in the direction crossing the first direction.
• the separated first insulating film and the separated second insulating film may be silicon oxide films, and the separated protective film may be a silicon nitride film.
• the film thickness of the separated first mask layer after forming the first openings may be larger than the film thickness of the separated second mask layer.
• the separated conductive layer below the isolation regions can be prevented from being removed.
• forming the separated gate insulating film may be performed by removing the separated first insulating film by using isotropic etching. The separated gate insulating film can easily be formed at center portions below the gate electrodes.
• the method may also include forming bit lines extending in the first direction in the semiconductor substrate, and defined by the second openings. Further, the method may also include forming word lines on the gate electrodes extending in a second direction that is a direction crossing the first direction. Furthermore, the separated charge storage layer may be made of either a polysilicon film or a silicon nitride film.
• the width of the separated second insulating film in the direction crossing the first direction can be made larger than the width of the separated gate insulating film in the direction crossing the first direction.
• the separated second insulating film and the separated gate insulating film can be formed aligned alternately in the first direction.
• tilting of the gate electrodes formed on the separated gate insulating film can be prevented.
• the gate electrodes are formed self-aligned to the separated second insulating film, tilting of the gate electrodes can be prevented.
• FIG. 1 is a cross-sectional view of a conventional flash memory
• FIG. 2 is a cross-sectional view illustrating a method for preventing charges from interfering with each other, in accordance with various embodiments of the present invention
• FIG. 3A is a cross-sectional view illustrating the formation of a gate insulating film in a method for manufacturing a separated charge storage layer, in accordance with various embodiments of the present invention
• FIG. 3B is a cross-sectional view illustrating the etching of a gate insulating film in a method for manufacturing a separated charge storage layer, in accordance with various embodiments of the present invention
• FIG. 3C is a cross-sectional view illustrating the formation of a separated charge storage layer in a method for manufacturing a separated charge storage layer, in accordance with various embodiments of the present invention.
• FIG.4 is a cross-sectional view illustrating exemplary problems that may occur when manufacturing the separated charge storage layer, in accordance with various embodiments of the present invention
• FIG. 5 is a top view of a flash memory, in accordance with various embodiments of the present invention.
• FIG. 6A is a cross-sectional view taken along the line A-A of a flash memory in accordance with various embodiments of the present invention.
• FIG. 6B is a cross-sectional view taken along the line B-B in FIG. 5, of a flash memory in accordance with various embodiments of the present invention.
• FIG. 6C is a cross-sectional view taken along the line C-C of a flash memory in accordance with various embodiments of the present invention.
• FIG. 6D is a cross-sectional view taken along the line D-D of a flash memory in accordance with various embodiments of the present invention.
• FIG. 7A illustrates a cross-sectional view taken along the line A-A of a flash memory during a first step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 7B illustrates a cross-sectional view taken along the line B-B of a flash memory during a first step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 7C illustrates a cross-sectional view taken along the line C-C of a flash memory during a first step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 8A illustrates a cross-sectional view taken along the line A-A of a flash memory during a second step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 8B illustrates a cross-sectional view taken along the line B-B of a flash memory during a second step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 8C illustrates a cross-sectional view taken along the line C-C of a flash memory during a second step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG.9A illustrates a cross-sectional view taken along the line A-A of a flash memory during a third step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 9B illustrates a cross-sectional view taken along the line B-B of a flash memory during a third step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 9C illustrates a cross-sectional view taken along the line C-C of a flash memory during a third step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 1OA illustrates a cross-sectional view taken along the line A-A of a flash memory during a fourth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 1OB illustrates a cross-sectional view taken along the line B-B of a flash memory during a fourth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 1OC illustrates a cross-sectional view taken along the line C-C of a flash memory during a fourth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 1 IA illustrates a cross-sectional view taken along the line A-A of a flash memory during a fifth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 1 IB illustrates a cross-sectional view taken along the line B-B of a flash memory during a fifth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 11C illustrates a cross-sectional view taken along the line C-C of a flash memory during a fifth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 12A illustrates a cross-sectional view taken along the line A-A of a flash memory during a sixth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 12B illustrates a cross-sectional view taken along the line B-B of a flash memory during a sixth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 12C illustrates a cross-sectional view taken along the line C-C of a flash memory during a sixth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 13A illustrates a cross-sectional view taken along the line A-A of a flash memory during a seventh step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 13B illustrates a cross-sectional view taken along the line B-B of a flash memory during a seventh step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 13C illustrates a cross-sectional view taken along the line C-C of a flash memory during a seventh step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 14A illustrates a cross-sectional view taken along the line A-A of a flash memory during a eighth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 14C illustrates a cross-sectional view taken along the line C-C of a flash memory during a eighth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 15A illustrates a cross-sectional view taken along the line A-A of a flash memory during a ninth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 15B illustrates a cross-sectional view taken along the line B-B of a flash memory during a ninth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 15C illustrates a cross-sectional view taken along the line C-C of a flash memory during a ninth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 15D illustrates a cross-sectional view taken along the line D-D of a flash memory during a ninth step in a method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 16A illustrates a cross-sectional view taken along the line A-A of a flash memory during a first step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 16B illustrates a cross-sectional view taken along the line B-B of a flash memory during a first step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 16C illustrates a cross-sectional view taken along the line C-C of a flash memory during a first step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 17A illustrates a cross-sectional view taken along the line A-A of a flash memory during a second step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 17B illustrates a cross-sectional view taken along the line B-B of a flash memory during a second step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 17C illustrates a cross-sectional view taken along the line C-C of a flash memory during a second step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 18A illustrates a cross-sectional view taken along the line A-A of a flash memory during a third step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 18B illustrates a cross-sectional view taken along the line B-B of a flash memory during a third step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 18C illustrates a cross-sectional view taken along the line C-C of a flash memory during a third step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 19A illustrates a cross-sectional view taken along the line A-A of a flash memory during a fourth step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 19B illustrates a cross-sectional view taken along the line B-B of a flash memory during a fourth step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 19C illustrates a cross-sectional view taken along the line C-C of a flash memory during a fourth step in an alternate method for manufacturing a flash memory in accordance with various embodiments of the present invention
• FIG. 2 a method for suppressing effects of the CBD by adopting a structure shown in FIG. 2 and controlling the movement of charges stored in the charge storage regions in a channel direction is depicted, in accordance with various embodiments.
• a gate insulating film 22 is provided over the semiconductor substrate 10 between the bit lines 18, that is at a center portion below the gate electrode 24.
• the charge storage layer 14 is provided in a separated manner. As described above, by providing the charge storage layer 14 in a separated manner with the gate insulating film 22 interposed, the movement of charges stored in the charge storage regions can be controlled in the channel direction, thereby effects of the CBD can be suppressed.
• FIG. 3A An example of a method for manufacturing of forming the separated charge storage layer 14 will be described with reference to FIG. 3A to FIG. 3C.
• the tunnel insulating film 12 and the top insulating film 16 drawings thereof are omitted for the sake of simplicity.
• the gate insulating film 22 is formed on the semiconductor substrate 10.
• the gate electrode 24 is formed on the gate insulating film 22.
• the gate insulating film 22 is etched from both side faces such that the gate insulating film 22 remains at the center portion below the gate electrode 24.
• FIG. 3C the separated charge storage layer 14 is formed in an area where the gate insulating film 22 is etched. Accordingly, the separated charge storage layer 14 with the gate insulating film 22 interposed can be formed.
• the gate electrode 24 when etching both side faces of the gate insulating film 22 as shown in FIG. 3B, the gate electrode 24 might tilt due to thinning of the width of the gate insulating film 22 as shown in FIG. 4.
• embodiments which can prevent tilting of a gate electrode when forming the gate insulating film 22 at a center portion below the gate electrode 24 will be described below.
• FIG. 5 is a top view of a flash memory according to one embodiment of the present invention.
• FIG. 6A is a cross-sectional view taken along the line A-A in FIG. 5
• FIG. 6B is a cross-sectional view taken along the line B-B in FIG. 5
• FIG. 6C is a cross-sectional view taken along the line C-C in FIG. 5
• FIG. 6D is a cross-sectional view taken along the line D-D in FIG. 5.
• bit lines 18 are shown through a separated second silicon oxide film 41, an interlayer insulating film 50, and the like.
• the bit lines 18 (which are N-type diffusion regions) are provided extending in a semiconductor substrate 10 which is a P-type silicon substrate.
• a separated gate insulating film 22 made of a silicon oxide film is provided on the semiconductor substrate 10 at center portions between the bit lines 18, a separated gate insulating film 22 made of a silicon oxide film is provided.
• a separated tunnel insulating film 12 and a separated charge storage layer 14, and a separated top insulating film 16 are sequentially provided with the separated gate insulating film 22 interposed.
• the separated tunnel insulating film 12 and the separated top insulating film 16 are made of silicon oxide films.
• the separated charge storage layer 14 is made of a polysilicon film. Thereby, a separated oxide polysilicon oxide (OPO) film 26 is composed.
• OPO oxide polysilicon oxide
• gate electrodes 24 made of polysilicon films are provided on the separated gate insulating film 22 and the separated OPO film 26 on the separated gate insulating film 22 and the separated OPO film 26, gate electrodes 24 made of polysilicon films are provided. A first silicon oxide film 39 is provided on side faces of the gate electrodes 24.. On the gate electrodes 24, word lines 20 made of polysilicon films electrically coupled to the gate electrodes 24 and extending crossing the bit lines 18 are provided. With reference to FIG. 6B and FIG. 6C, the separated gate insulating film 22 is provided at center portions below the gate electrodes 24 in a width direction of the bit lines 18.
• grooves are provided in the semiconductor substrate 10 between the word lines 20 (that is, between the gate electrodes 24) and between the bit lines 18.
• a separated second insulating film 30 made of a silicon oxide film is provided on the semiconductor substrate 10 so as to be embedded in the grooves.
• a separated protective film 32 made of a silicon nitride film composed of a material having different etching rate than that of the separated second insulating film 30 is provided.
• the width of the separated second insulating film 30 in the width direction of the bit lines 18 is formed to be larger than the width of the separated gate insulating film 22 in the width direction of the bit lines 18.
• an upper surface of the separated second insulating film 30 is formed at a higher level than an upper surface of the separated gate insulating film 22.
• the upper surface of the separated second insulating film 30 and the upper surface of the gate electrodes 24 are provided on the same plane.
• the separated second silicon oxide film 41 is provided on the bit lines 18.
• the interlayer insulating film 50 made of a silicon oxide film is provided between the word lines 20.
• FIG. 7A, FIG. 8A, FIG. 9A, FIG. 1OA, FIG. 1 IA, FIG. 12 A, FIG. 13 A, FIG. 14A and FIG. 15A are cross-sectional views corresponding to the line A-A in FIG. 5.
• FIG. 7B, FIG. 8B, FIG. 9B, FIG. 1OB, FIG. 1 IB, FIG. 12B, FIG. 13B, FIG. 14B and FIG. 15B are cross-sectional views corresponding to the line B-B in FIG. 5.
• FIG. 13C, FIG. 14C and FIG. 15C are cross-sectional views corresponding to the line C-C in FIG. 5C.
• FIG. 15D is a cross-sectional view corresponding to the line D-D in FIG. 5.
• a separated first insulating film 34 made of a silicon oxide film and having a film thickness of 25nm is formed on the semiconductor substrate 10 that is a P-type silicon substrate by using a thermal oxidation method.
• a separated conductive layer 36 made of a polysilicon film is formed on the separated first insulating film 34 by using a chemical vapor deposition (CVD) method.
• CVD chemical vapor deposition
• a separated first mask layer 38 made of a silicon nitride film and having a film thickness of 50 nm is formed on the separated conductive layer 36, by using the CVD method,.
• a photoresist (not shown) having a stripe shape extending in a first direction (direction in which the bit lines 18 are to be extended) is formed on the separated first mask layer 38.
• the separated first mask layer 38 is removed by using a reactive ion etching (RIE) method. Accordingly, the separated first mask layer 38 is formed in a stripe shape extending in the first direction.
• RIE reactive ion etching
• a separated second mask layer 40 made of a silicon oxide film is formed on the separated conductive layer 36, by using the CVD method so as to cover the separated first mask layer 38.
• the separated second mask layer 40 is polished by using a chemical mechanical polishing (CMP) method so as to expose a surface of the separated first mask layer 38.
• CMP chemical mechanical polishing
• a stripe-shaped photoresist 45 is formed on the separated first mask layer 38 and the separated second mask layer 40, extending in a width direction of the separated first mask layer 38 and the separated second mask layer 40 (a second direction that is a direction crossing the first direction).
• the separated second mask layer 40 is removed by using the RIE method. Accordingly, the separated second mask layer 40 remains, being isolated in the first direction, interposing in the separated first mask layer 38 on the separated conductive layer 36.
• the separated second mask layer 40 is formed in isolation regions 35 isolated and interposing in the separated first mask layer 38 in the first direction. That is, the separated first mask layer 38 and the separated second mask layer 40 form a lattice-shaped mask.
• first openings 42 that penetrate through the separated conductive layer 36 and the separated first insulating film 34 are formed.
• grooves 28 are formed in the semiconductor substrate 10 below the first openings 42.
• the film thickness Tl of the separated first mask layer 38 after the first openings 42 and the grooves 28 are formed is larger than the film thickness T2 of the separated second mask layer 40.
• the separated first insulating film 34 and the separated second mask layer 40 both have the same material as that of the silicon oxide film, when removing the separated first insulating film 34 so as to form the first openings 42, the separated second mask layer 40 used as a mask is also removed. However, since the film thickness of the separated first insulating film 34 is 25 nm and the film thickness of the separated second mask layer 40 is 50 nm, the separated second mask layer 40 remains, and the separated conductive layer 36 below the separated second mask layer 40 are not removed. As described above, so as not to remove the separated conductive layer 36 below the separated second mask layer 40, the film thickness of the separated second mask layer 40 is preferable to be set in advance.
• a silicon nitride film is deposited on the semiconductor substrate 10 by using the CVD method,. Accordingly, the separated protective film 32 made of a silicon nitride film is formed on side faces of the first openings 42 and inner surfaces of the grooves 28.
• a silicon oxide film is completely deposited on the semiconductor substrate 10.
• the CMP method the silicon oxide film is polished so that the surface of the separated first mask layer 38 is exposed.
• the separated second insulating film 30 made of a silicon oxide film is formed so as to be embedded in the first openings 42 and the grooves 28. Also, the separated second insulating film 30 is formed in the isolation regions 35 isolated and interposing in the separated first mask layer 38 in the first direction.
• the separated second insulating film 30 As a mask, the separated first mask layer 38, the separated conductive layer 36, and the separated first insulating film 34 are removed by using the RIE method. Accordingly, second openings 46 that penetrate through the separated first insulating film 34 and the separated conductive layer 36 are formed. Also, in between the second openings 46, the gate electrodes 24 composed of the separated conductive layer 36 having a length of about 90 nm that correspond to the channel length L are formed.
• the separated first insulating film 34 formed below the gate electrodes 24 is removed through the second openings 46 by using a wet etching method by fluorinated acid,. Accordingly, undercut portions 48 having a depth of about 30 nm from side faces of the gate electrodes 24 are formed below both edges of the gate electrodes 24, which are regions where the separated first insulating film 34 is removed.
• the separated gate insulating film 22 composed of the separated first insulating film 34 and having a width of about 30 nm in the second direction is formed at center portions below the gate electrodes 24,.
• the separated tunnel insulating film 12 and the separated top insulating film 16 made of silicon oxide films are formed in the undercut portions 48 by using a thermal oxidation method.
• a silicon oxide film (first silicon oxide film 39) is formed also on side faces of the gate electrodes 24 and the like.
• LP-CVD low pressure chemical vapor deposition
• a polysilicon film is formed on the semiconductor substrate 10 so as to cover the gate electrodes 24 and the separated second insulating film 30.
• a separated polysilicon film is formed in the undercut portions 48 between the separated tunnel insulating film 12 and the separated top insulating film 16.
• the polysilicon film formed on the side faces of the gate electrodes 24 and the like are oxidized so as to be made into the first silicon oxide film 39 by using a thermal oxidation method. Since the separated polysilicon film formed in the undercut portions 48 between the separated tunnel insulating film 12 and the separated top insulating film 16 is located at recessed area, the separated polysilicon film is hardly oxidized, whereby the separated polysilicon film remains as is and becomes the separated charge storage layer 14.
• arsenic ion is implanted through the second openings 46 into the semiconductor substrate 10. Accordingly, the bit lines 18 that are N-type diffusion regions defined by the second openings 46 are formed extending in the first direction in the semiconductor substrate 10.
• the separated second silicon oxide film 41 is formed on the semiconductor substrate 10 so as to be embedded in the second openings 46 by using the high- density plasma CVD method. Thereafter, in order to expose the upper surfaces of the gate electrodes 24, the separated second silicon oxide film 41 and the like are polished by using the CMP method.
• the top surfaces of the gate electrodes 24 may be exposed by using dry etching, wet etching, and the like.
• the word lines 20 made of polysilicon films that are electrically coupled to the gate electrodes 24 and extended in the second direction are formed. That is, the word lines 20 are extended crossing the bit lines 18.
• the interlayer insulating film 50 made of a silicon oxide film is formed between the word lines 20.
• the separated first insulating film 34 and the separated conductive layer 36 are sequentially formed on the semiconductor substrate 10.
• the separated first mask layer 38 is formed on the separated conductive layer 36 so as to extend in the first direction (extending direction of the bit lines 18).
• the separated second mask layer 40 is formed in the isolation regions 35 isolated and interposing in the separated first mask layer 38 in the first direction.
• FIG. 1OA to FIG. 1OC by using the separated first mask layer 38 and the separated second masks layer 40 as a mask, the separated conductive layer 36 and the separated first insulating film 34 are removed to form the first openings 42.
• the separated second insulating film 30 is formed in the first openings 42 and the isolation regions 35.
• the separated first mask layer 38, the separated conductive layer 36, and the separated first insulating film 34 are removed to form the second openings 46.
• the gate electrodes 24 composed of the separated conductive layer 36 are formed between the second openings 46.
• the separated first insulating film 34 formed below the gate electrodes 24 is removed, thereby the separated gate insulating film 22 composed of the separated first insulating film 34 is formed at center portions below the gate electrodes 24.
• the width of the separated second insulating film 30 in the width direction of the bit lines 18 can be formed larger than the width of the separated gate insulating film 22 in the width direction of the bit lines 18.
• the separated second insulating film 30 and the separated gate insulating film 22 can be formed aligned alternately in the bit lines 18 extending direction (first direction). Accordingly, as explained in FIG. 13A to FIG.
• the separated second insulating film 30 is formed so as to be embedded in the first openings 42. That is, the upper surface of the separated second insulating film 30 is formed higher than the upper surface of the separated first insulating film 34. Accordingly, the gate electrodes 24 formed on the separated gate insulating film 22 can be brought into contact with the separated second insulating film 30. Consequently, even in the case where the separated gate insulating film 22 having a small width is formed at center portions below the gate electrodes 24, tilting of the gate electrodes 24 can be prevented.
• the gate electrodes 24 can be formed self-aligned to the separated second insulating film 30. Accordingly, contacting area of the gate electrodes 24 and the separated second insulating film 30 can be maximized. Consequently, tilting of the gate electrodes 24 can be prevented.
• the separated first insulating film 34 formed below the gate electrodes 24 is removed, thereby the undercut portions 48 are formed below both edges of the gate electrodes 24. Accordingly, center portions below the gate electrodes 24, the separated gate insulating film 22 composed of the separated first insulating film 34 is formed.
• the separated charge storage layer 14 is formed in the undercut portions 48, that are regions where the separated first insulating film 34 formed below the gate electrodes 24 is removed. Accordingly, the separated charge storage layer 14 can be formed with the separated gate insulating film 22 interposed in the width direction of the bit lines 18. Consequently, the charge storage region stored with charges can be separated, whereby effects of the CBD can be suppressed.
• the grooves 28 are formed below the first openings 42 on the semiconductor substrate 10.
• the separated second insulating film 30 is formed so as to be embedded in the grooves 28. Accordingly, the separated second insulating film 30 can be formed in the semiconductor substrate 10 between the bit lines 18 and between the gate electrodes 24. In other words, the separated second insulating film 30 can be formed between the bit lines 18 in the periphery of the gate electrodes 24 on the semiconductor substrate 10. Consequently, fringe current that flows in the periphery of the gate electrodes 24 on the semiconductor substrate 10 can be suppressed. The fringe current may cause malfunction when reading data and the like. Therefore, by preventing the fringe current, data reading performance can be enhanced.
• the separated protective film 32 is formed on side faces of the first openings 42, and thereafter, the separated second insulating film 30 is formed in the first openings 42. As a result, the separated protective film 32 is formed on side faces of the separated second insulating film 30.
• the separated first insulating film 34 and the separated second insulating film 30 are made of silicon oxide films.
• the separated protective film 32 is made of a silicon nitride film.
• the width of the separated second insulating film 30 in the width direction of the bit lines 18 can easily be made larger than the width of the separated gate insulating film 22 in the width direction of the bit lines 18. Accordingly, when removing the separated first insulating film 34 formed below the gate electrodes 24 to form the separated gate insulating film 22, a material of the separated protective film 32 is preferable to be a material that is less likely to be removed than the separated first insulating film 34.
• a material of the separated second insulating film 30 is preferable to be a material that is less likely to be removed than the separated first insulating film 34.
• the width of the separated second insulating film 30 in the width direction of the bit lines 18 can easily be made larger than the width of the separated gate insulating film 22 in the width direction of the bit lines 18 without forming the separated protective film 32 on side faces of the separated second insulating film 30. Accordingly, the manufacturing process can be shortened and simplified.
• the film thickness of the separated first mask layer 38 after forming the first openings 42 and the grooves 28 may be preferable to be larger than the film thickness of the separated second mask layer 40.
• the film thickness of the separated second insulating film 30 formed in the isolation regions 35 can be made thick.
• FIG. 12A to FIG. 12C by using the separated second insulating film 30 as a mask, when removing the separated first insulating film 34, the separated conductive layer 36, and the separated first mask layer 38, the separated conductive layer 36 below the isolation regions 35 can be prevented from being removed.
• the separated first insulating film 34 formed below the gate electrodes 24 is removed, and thereby the separated gate insulating film 22 composed of the separated first insulating film 34 is formed at center portions below the gate electrodes 24. Since the wet etching by fluorinated acid is isotropic etching, the separated first insulating film 34 is etched from both side faces in a similar manner. Thus, the separated gate insulating film 22 can easily be formed at center portions below the gate electrodes 24. Accordingly, the process of forming the separated gate insulating film 22 is preferable to be adopted in a case when removing the separated first insulating film 34 formed below the gate electrodes 24 through the second openings 46 by using isotropic etching.
• the separated second insulating film 30 is hardly removed since the separated second insulating film 30 is covered by the separated protective film 32, whereby the undercut portions 48 are hardly formed below both edges of the separated second insulating film 30. That is, the charge storage layer 14 is hardly formed below both edges of the separated second insulating film 30.
• the charge storage layer 14 adjacent to each other in the extending direction of the bit lines 18 is formed in a separated manner.
• the separated charge storage layer 14 is formed of a polysilicon film, charges can be stored locally below the gate electrodes 24.
• the separated charge storage layer 14 is not limited to a polysilicon film, and for example, a silicon nitride film and the like may be used. Other materials which store charges may also be used.
• the separated second mask layer 40 may be either removed or unremoved as long as the separate secon insu a ng i m s orme n t e so at on reg ons on t e separated conductive layer 36.
• the separated second insulating film 30 is formed after a silicon nitride film is completely deposited on the semiconductor substrate 10.
• a separated multi-layered film composed of a separated silicon nitride film (separated protective film 32) and a separated silicon oxide film (separated second insulating film 30) is formed in the isolation regions 35.
• a polishing amount can be controlled by detecting the difference of the material to be polished.
• the silicon nitride film can be used as a stopper film. Accordingly, in a case where the separated multi-layered film composed of the separated silicon nitride film and the separated silicon oxide film is formed on the separated conductive layer 36 (that is, on the gate electrodes 24) as in the first embodiment, a polishing amount of polishing by the CMP method can be controlled further precisely. Consequently, it may be preferable to completely remove the separated second mask layer 40 formed in the isolation regions 35 after forming the first openings 42.
• FIG. 16A, FIG. 17A, FIG. 18A, and FIG. 19A are cross- sectional views corresponding to the line A-A in FIG. 5.
• FIG. 16B, FIG. 17B, FIG. 18B, and FIG. 19B are cross-sectional views corresponding to the line B-B in FIG. 5.
• FIG. 16C, FIG. 17C, FIG. 18C, and FIG. 19C are cross-sectional views corresponding to the line C-C in FIG. 5.
• the manufacturing processes explained with reference to FIG. 7A to FIG. 9C are initially performed.
• the separated conductive layer 36 and the separated first insulating film 34 are removed by using the RIE method. Accordingly, the first openings 42 penetrating through the separated conductive layer 36 and the separated first insulating film 34 are formed. . ⁇ , as pure matter . , font , . ...
• the silicon nitride film is deposited on the semiconductor substrate 10 by using the CVD method, and thereafter, the silicon nitride film is completely etched by using the RIE method. Accordingly, the separated protective film 32 composed on a silicon nitride film is formed on side faces of the first openings 42 and the like.
• the semiconductor substrate 10 below the first openings 42 is oxidized by a thermal oxidation method, and thereby the separated third insulating film 52 made of a silicon oxide film is formed on the surface of the semiconductor substrate 10.
• the separated conductive layer 36 is covered by the separated protective film 32 and the like, the separated conductive layer 36 is not oxidized.
• the separated second insulating film 30 made of a silicon oxide film is formed so as to be embedded in the first openings 42 and so as to cover the separated first mask layer 38 by using a high density plasma CVD method. Thereafter, by using the CMP method, the separated second insulating film 30 is polished so that the surface of the separated first mask layer 38 is exposed.
• the manufacturing processes explained with reference to FIG. 12A to FIG. 15D are preformed.
• the semiconductor substrate 10 is oxidized, and thereby the separated third insulating film 52 is formed on the surface of the semiconductor substrate 10 on the lower side of the first openings 42. Accordingly, the separated third insulating film 52 is formed on the surface of the semiconductor substrate 10 between the bit lines 18 in the periphery of the gate electrodes 24. Thus, the fringe current that flows in the semiconductor substrate 10 in the periphery of the gate electrodes 24 can be suppressed.
• the semiconductor substrate 10 may be oxidized by a plasma oxidation method, a radical oxidation method, or other methods.

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