CN1947240A - 制造芯片和相关支撑的方法 - Google Patents

制造芯片和相关支撑的方法 Download PDF

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Publication number
CN1947240A
CN1947240A CNA2005800134753A CN200580013475A CN1947240A CN 1947240 A CN1947240 A CN 1947240A CN A2005800134753 A CNA2005800134753 A CN A2005800134753A CN 200580013475 A CN200580013475 A CN 200580013475A CN 1947240 A CN1947240 A CN 1947240A
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CN
China
Prior art keywords
support
chip
layer
brick bat
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005800134753A
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English (en)
Chinese (zh)
Inventor
B·吉斯勒
O·雷萨克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN1947240A publication Critical patent/CN1947240A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
CNA2005800134753A 2004-04-27 2005-04-25 制造芯片和相关支撑的方法 Pending CN1947240A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0404437 2004-04-27
FR0404437A FR2869455B1 (fr) 2004-04-27 2004-04-27 Procede de fabrication de puces et support associe

Publications (1)

Publication Number Publication Date
CN1947240A true CN1947240A (zh) 2007-04-11

Family

ID=34945110

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005800134753A Pending CN1947240A (zh) 2004-04-27 2005-04-25 制造芯片和相关支撑的方法

Country Status (7)

Country Link
US (1) US7544586B2 (fr)
EP (1) EP1756864B9 (fr)
JP (1) JP4782107B2 (fr)
KR (1) KR100836289B1 (fr)
CN (1) CN1947240A (fr)
FR (1) FR2869455B1 (fr)
WO (1) WO2005106948A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054854A (zh) * 2009-10-30 2011-05-11 乐金显示有限公司 有机电致发光显示设备及其制造方法
CN103137140A (zh) * 2011-11-24 2013-06-05 新科实业有限公司 光源芯片、热促进磁头及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7808082B2 (en) * 2006-11-14 2010-10-05 International Business Machines Corporation Structure and method for dual surface orientations for CMOS transistors
US7858493B2 (en) * 2007-02-23 2010-12-28 Finisar Corporation Cleaving edge-emitting lasers from a wafer cell
DE102008038342B4 (de) * 2008-08-19 2015-08-06 Infineon Technologies Austria Ag Halbleiterbauelement mit Randbereich, in dem eine Zone aus porösem Material ausgebildet ist und Verfahren zu dessen Herstellung und Halbleiterscheibe
JP5127669B2 (ja) * 2008-10-31 2013-01-23 パナソニック株式会社 半導体ウェハ
FR3058830B1 (fr) * 2016-11-14 2018-11-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation collective d’une pluralite de puces optoelectroniques
IL254078A0 (en) 2017-08-21 2017-09-28 Advanced Vision Tech A V T Ltd Method and system for creating images for testing
FR3087936B1 (fr) * 2018-10-24 2022-07-15 Aledia Dispositif electronique

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029280A (fr) * 1973-07-20 1975-03-25
JPS5848172A (ja) 1981-09-18 1983-03-22 Fujitsu Ltd 多言語間翻訳装置
JPS59172740A (ja) * 1983-03-22 1984-09-29 Mitsubishi Electric Corp 半導体ウエ−ハの分割方法
JPS60108745A (ja) 1983-11-18 1985-06-14 Ngk Insulators Ltd 電気化学的装置
JPH06105754B2 (ja) * 1985-05-21 1994-12-21 株式会社フジクラ 半導体チツプの製造方法
US5393706A (en) * 1993-01-07 1995-02-28 Texas Instruments Incorporated Integrated partial sawing process
JPH08107193A (ja) * 1994-09-30 1996-04-23 Kyushu Komatsu Denshi Kk Soi基板の製造方法
US5904548A (en) * 1996-11-21 1999-05-18 Texas Instruments Incorporated Trench scribe line for decreased chip spacing
JP2000298818A (ja) * 1999-04-12 2000-10-24 Tdk Corp 多面付素子の加工方法およびスライダの加工方法
JP3532788B2 (ja) * 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP4320892B2 (ja) * 2000-01-20 2009-08-26 株式会社デンソー 接合基板の切断方法
JP2001345289A (ja) 2000-05-31 2001-12-14 Nec Corp 半導体装置の製造方法
US6933212B1 (en) * 2004-01-13 2005-08-23 National Semiconductor Corporation Apparatus and method for dicing semiconductor wafers
US8426293B2 (en) * 2004-07-09 2013-04-23 Semiconductor Energy Laboratory Co., Ltd. IC chip and its manufacturing method
US7452739B2 (en) * 2006-03-09 2008-11-18 Semi-Photonics Co., Ltd. Method of separating semiconductor dies

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054854A (zh) * 2009-10-30 2011-05-11 乐金显示有限公司 有机电致发光显示设备及其制造方法
US8858286B2 (en) 2009-10-30 2014-10-14 Lg Display Co., Ltd. Organic electroluminescent display device and method of fabricating the same
CN102054854B (zh) * 2009-10-30 2014-11-26 乐金显示有限公司 有机电致发光显示设备及其制造方法
CN103137140A (zh) * 2011-11-24 2013-06-05 新科实业有限公司 光源芯片、热促进磁头及其制造方法

Also Published As

Publication number Publication date
JP2007535158A (ja) 2007-11-29
US20050236700A1 (en) 2005-10-27
EP1756864B9 (fr) 2013-02-13
WO2005106948A1 (fr) 2005-11-10
KR20070004056A (ko) 2007-01-05
US7544586B2 (en) 2009-06-09
EP1756864A1 (fr) 2007-02-28
JP4782107B2 (ja) 2011-09-28
FR2869455A1 (fr) 2005-10-28
FR2869455B1 (fr) 2006-07-14
EP1756864B1 (fr) 2012-08-01
KR100836289B1 (ko) 2008-06-09

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