CN1945804A - 制作具有露出的翼片的模制阵列封装器件的方法和结构 - Google Patents

制作具有露出的翼片的模制阵列封装器件的方法和结构 Download PDF

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CN1945804A
CN1945804A CNA2006101540464A CN200610154046A CN1945804A CN 1945804 A CN1945804 A CN 1945804A CN A2006101540464 A CNA2006101540464 A CN A2006101540464A CN 200610154046 A CN200610154046 A CN 200610154046A CN 1945804 A CN1945804 A CN 1945804A
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sign
wire
leads
molded
electronic chip
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CN100543952C (zh
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小詹姆斯·P·莱特蔓
肯特·L·凯姆
乔斯弗·K·弗蒂
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Semiconductor Components Industries LLC
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Abstract

在一个实施例中，用于制作包括附着电子芯片于阵列引线框架的模制扁平封装类型的封装的方法，该封装包括包含翼片部分的多个细长的标志部分和多条引线。该方法还包括连接电子芯片至特定的引线，然后模制该阵列引线框架，同时让引线的一部分露出以形成模制阵列结构。然后分隔该模制阵列结构，以提供具有露出的引线和露出的翼片部分的模制扁平封装类型的封装，所述露出的引线用于插入安装。在一个替代的实施例中，该分隔步骤提供了包含露出的翼片部分的不含引线配置。

Description

制作具有露出的翼片 的模制阵列封装器件的方法和结构
技术领域
本申请一般地涉及电子器件，而且更具体地，涉及功率半导体封装和组装的方法。
背景技术
随着便携电子产品的小型化，手持消费产品的市场势不可挡。目前，主要受便携式电话和数码助理市场的驱动，这些器件的生产商不断地受到了缩小体积和要求更多类似PC功能的挑战。这种挑战给表面安装元件的生产商压力，以便将他们的产品设计成达到尽可能最小的面积。通过这样做，这使得便携电子产品的设计者能够在器件中结合额外的功能而无需增加总的产品尺寸。
在芯片级封装(CSP)技术领域中，生产商努力将封装尺寸尽可能地接近半导体芯片的尺寸。电子工业已经接受了电子设备工程联合委员会(JEDEC)定义的方块扁平封装(QFP)和无引线方块扁平封装(QFN)概要(outlines)作为低成本的芯片级封装的好选择。在典型的QFP和QFN封装中，半导体芯片的下表面附着于金属引线框架上。然后利用导线键合将位于芯片前侧上的电路连接到引线框架的每条引线上。接着，芯片和引线框架由环氧树脂密封以形成组装元件。
图1示出了常规的包括引线框架11的QFP封装10的部分截面图。引线框架11包括用于支撑半导体芯片14和引线16的标志(flag)部分13。导线键合17将半导体芯片14与引线16连接。除了引线16的一部分以外，环氧树脂层19覆盖半导体芯片14和引线框架11，所述引线16从该封装的侧面以鸥形翼(gull wing)的形状延伸。尽管只示出了QFP封装10的一部分，但是QFP封装典型地为方形或矩形，导线16自封装的所有的四个侧面延伸。
图2示出了常规的包括引线框架21的QFP封装20的部分截面图。引线框架21包括用于支撑半导体芯片14和引线26的标志(flag)部分23。导线键合17将半导体芯片14与引线26连接。环氧树脂层19覆盖半导体芯片14和引线框架21的一部分，同时让标志23和引线26的下面的部分露出出来。在该QFP封装中，引线(例如，引线26)终止在该封装的边缘以提供一较小的封装覆盖区(footprint)。尽管只示出了QFP封装20的一部分，但是QFP封装典型地为方形或矩形，引线存在于该封装的下表面的所有四个侧面。图3示出了器件20的等轴剖开图。双扁平无引线封装(QFN)类似于QFN的另外一种芯片级封装，除了DFN仅在封装下表面的两个相对侧面上具有引线。
对于QFP、QFN和DFN封装有几个优点，包括：管芯尺寸与封装覆盖区比大、容易组件的矩阵引线框架阵列和已经建立的自动的组装工具。然而，存在几个与这些封装相关的问题，包括：对于高功率器件应用热传导能力差，而且在将该封装件附着于包括热沉和印刷电路板的下级组件时，安装选项非常有限。
因此，需要一种在已有的芯片级组装平台上可制造的封装结构和组装方法，其使用引线框架(如，QFP/QFN/DFN平台)，其支持高功率应用，支持多管芯选项，并且其具有用于连接下级组件的更加灵活的选项。
发明内容
根据本发明的一方面，提供一种制作模制阵列封装器件的方法，包括以下步骤：提供具有包含翼片部分的多个标志和与该多个标志隔开的多条引线的主引线框架；将电子芯片安装于该标志部分；耦接该电子芯片至该多条引线；密封该主引线框架，同时让该多条引线的一部分露出以提供模制阵列封装组件；并且将该模制阵列封装组件分隔开为单独的模制封装器件。
根据本发明的另一方面，提供一种制作扁平封装结构的工艺，包括步骤：提供具有包含翼片的多个细长的标志和多条引线的阵列引线框架；将电子芯片附着于该细长的标志部分；耦接该电子芯片至该多条引线；在该细长的标志部分的一部分上形成连续的密封层，同时让该翼片和该多条引线的一部分露出以提供模制组件；并且通过穿过该多个细长的标志部分、穿过该连续的密封层、并且穿过该多条引线进行分隔，将该模制组件分割成单独的封装件，从而提供具有露出的翼片部分的扁平封装结构。
根据本发明的另一方面，提供一种多芯片扁平封装器件，包括：具有翼片部分的第一标志；附着于该第一标志的第一电子芯片；与该第一标志隔开的第一多条引线，其中所述第一电子芯片耦接至该导电引线；与该第一多条引线隔开的第二标志；与该第二管芯附着叶片隔开的第二多条导电引线；附着于该第二管芯附着叶片并且耦接至第一和第二多条导电引线的第二电子芯片；覆盖该第一标志、该第一电子芯片和第一导电引线的一部分从而形成第一扁平封装器件的第一密封层；和覆盖该第二标志、该第二电子芯片和第一导电引线的其它部分从而形成第二扁平封装器件的第二密封层，其中所述第一导电引线的剩余部分在第一和第二扁平封装器件之间露出，并且其中第一导电引线中的至少一条将第一和第二扁平封装器件连接起来。
根据本发明的另一方面，提供一种扁平封装半导体器件，包括：具有翼片部分的标志；基本上共面并且与标志部分隔开的导电引线；耦接至该标志和该导电引线的半导体器件；以及覆盖该标志和半导体器件的经分割的密封层，其中所述翼片部分露出。
附图说明
图1说明了现有技术的方块扁平封装(QFP)封装件的一部分截面图；
图2说明了现有技术的方块扁平封装无引线(QFN)封装件的一部分截面图；
图3说明了图2的QFN封装件的等轴的和剖开的示意图；
图4说明了根据本发明的模制阵列封装的截面图；
图5说明了根据本发明在制造的中间阶段的组件结构的一部分顶视图；
图6说明了在根据本发明的下一处理中的图5的组件结构的顶视图；
图7说明了根据本发明的用于密封图5的组件结构的模制盖设计的概要的顶视图；
图8说明了在根据本发明的下一处理后的图6和7的组件结构的顶视图；
图9说明了根据本发明的一个实施例的翼片安装模制阵列封装；
图10说明了根据本发明的另一个实施例的翼片安装模制阵列封装的顶视图；
图11说明了根据本发明的另一个实施例的翼片安装模制阵列封装的顶视图；
图12说明了根据本发明的再另一个实施例的翼片安装模制阵列封装的顶视图；
图13说明了根据本发明的另一个实施例在制造的中间步骤的模制阵列封装结构的截面图；
图14说明了根据本发明的再另一个实施例在制造的中间步骤的模制阵列封装结构的截面图；
图15说明了根据本发明在制造的早期步骤时的用于制造图13和图14的封装件的组件结构；
图16说明了根据本发明具有翼片安装的多芯片模制阵列封装；
图17说明了根据本发明的另一个实施例的具有翼片安装的多芯片模制阵列封装；
图18说明了根据本发明的附着于下级组件的图17的多芯片模制阵列封装的侧面图；
图19说明了根据本发明的附着于不同的下级组件的图16的多芯片模制阵列封装的侧面图；
图20说明了根据本发明在制造的中间步骤的用于制造图16和17的封装件的组件结构的顶视图；
图21说明了根据本发明下一步处理后的图20的组件结构的顶视图；以及
图22说明了根据本发明下一步处理后的图21的组件结构的顶视图。
具体实施方式
为了容易理解，附图中的元件不一定按比例绘制，而且在所有的各附图中如果合适则使用类似的元件编号，以表示相同或类似的元件。
图4说明了根据本发明的模制阵列封装、模制结构、扁平封装结构或封装组件40。示出具有模制器件41和42两个例子的封装组件40。器件41和42均分别包括引线框架或导电引线框架46和47。引线框架46和47各具有标志部分或管芯附着叶片(paddle)51，其包括露出的翼片52。翼片52是与标志部分51成一体的露出部分或凸出部分，提供翼片用来将器件41和42附着于下级的组件，下级的组件包括，但并不局限于热沉、箱体、印刷电路板等。在该实施例所示，露出的翼片52提供有可选的通孔53。
导电引线框架46还包括按不含引线或无引线配置形成的导电引线57a，其将根据本发明在下面进行更加详细的解释。导电引线47包括按含引线或插入安装的配置形成的导电引线57b，其将根据本发明在下面进行更加详细的解释。
器件41和42各包含采用附着层61附着在标志部分51上的电子芯片或器件59。举例来说，电子芯片59可以包括功率MOSFET、双极型功率晶体管、绝缘栅双极型晶体管、晶闸管、二极管、传感器、光学器件，并且还可以包括集成逻辑器件或其他功能。作为进一步的例子，附着层61包括焊料或高传导性的环氧树脂材料。
连接结构将电子芯片59电连接到导电引线。例如，导电夹片或条62将器件41的电子芯片耦合至导电引线57a，同时导线键合63将器件42的电子芯片59耦接至导电引线57b。当使用夹片或条，焊料或导电环氧树脂适接用来将夹片或条附着在引线57a和电子芯片59上。
密封层66包围或覆盖器件41和42的一部分，但是不覆盖露出的翼片部分52、通孔53或引线57b。例如，密封层66包括塑料环氧树脂材料。虚线67代表一分隔线，用来在后续步骤中将器件41和42分割(singulating)成单独的器件。
图5示出根据本发明在制造的中间阶段的组件结构或副组件71的部分顶视图。结构71包括阵列引线框架或主引线框架72。举例来说，主引线框架72包括如下材料的单一标准化学碾压或压印的片构成：铜合金(例如TOMAC4、TAMAC5、2ZFROFC或CDA194)、镀铜的铁/镍合金(例如镀铜的合金42)、镀覆的铝、镀覆的塑料等。镀覆材料包括铜、银或多层镀覆镍-钯和金等。仍然以举例的方式，配置主引线框架72，使其与标准的方块扁平封装组件工具相兼容。
主引线框架72包括标志阵列或多个标志、细长的标志部分或管芯附着叶片(paddle)51。电子芯片59附着在标志部分51上，并且还使用例如连接导线或导线键合63或导电夹片62，与多个引线57连接或耦接。举例来说，使用自动的/可编程的拾取和放置工具，电子芯片59被放置在细长的标志51上。在早期步骤中，将焊料浆料或环氧树脂膜放置在细长的标志51上以提供附着层61，然后将电子芯片59放置在附着层61上。接着，通过固化工艺放置该组件以固化或回流附着层61来形成电子芯片59和细长的标志部分51之间的导线键合。可选地，主引线框架72被预先镀覆焊料或预先覆盖导电环氧树脂。可选地，电子芯片59包括诸如在一个表面上形成了电镀铅/锡层或环氧树脂层的焊料附着层，并且例如以晶片的形式而被施加。
标志部分51还包括具有通孔53的翼片部分52。在一个实施例中，每个标志部分51包括位于主引线框架72的中心线77的相对侧的两个通孔53，这也是图4中所示的分隔线67的例子。在一个实施例中，引线57邻近主引线框架72的外部78，并且形成或提供主引线框架72而不含、没有或不依赖于环氧树脂模具坝条(dam-bars)。此外，提供或形成主引线框架72，使得引线57的顶表面与标志部分51的顶表面基本上共面或尽可能平整，如图4所示。在可选实施例中，耦接器件79被附加在邻接的标志51之间，如图5所示。举例来说，耦接器件79包括为避免静电放电事件而提供保护的电容器件。
图6示出了根据本发明在下一处理中的组件结构71的顶视图。在这个步骤中，组件结构71位于如转移模制装置的模制设备中。固态树脂片被放置在精选装置(cull)或坩锅83中。当加热坩锅83来融化固态树脂片，迫使液化的树脂材料从坩锅83穿过流道86流到的模制腔中以形成连续的密封层或密封层66，同时根据本发明，让引线57的一部分、翼片52和通孔53露出或没有密封。应当理解，在一个实施例中，翼片51和引线57下表面的(即，该表面相对于电子芯片59安装于其上的表面)没有密封，以提供在后续组装操作中的电接触或连接。
图7示出了用于利用本发明形成狭缝模制阵列封装(MAP)组件的模制盖设计88的概要的一个示例的顶视图。模制盖88包括容纳标志51的一部分和引线71的一部分的空腔89。模制盖88还包括固体部分91，其覆盖或接触引线57的其他部分以及标志51的其他部分，使这些部分不被密封。箭头92代表在模制工艺中密封材料的流动方向的例子。
图8示出了根据本分明包括密封的或钝化的组件结构71的模制阵列封装组件40的顶视图。封装组件40包括多条露出的引线57和多个具有通孔53的露出的翼片52。分割线(singulation lines)67、103、104、107和108代表根据本发明为了将模制阵列封装组件40分隔为单独的模制阵列封装件或结构的可选分隔位置。
线103是水平的或第一方向切线，其提供包括图11和12中所示的封装41和42的单个模制阵列封装。线104是水平的或第一方向切线，其提供包括图9和10中所示的封装410和402的多芯片模制阵列封装。线67代表通过细长的标志部分51的垂直或第二方向的切线。线107代表垂直或第二方向的切线，其提供如图10和12中所示的封装420和42的翼片安装扁平封装无引线模制阵列封装。线108代表垂直或第二方向的切线，其提供如图9和11中所示的封装410和41的翼片安装扁平封装含引线或单引线(即，引线只在一个侧面上)的模制阵列封装。含引线的封装41和410具有露出的引线，该引线向外延伸以提供与插入安装PC板级组件性能相兼容的封装类型。使用例如常规的切割分片、锯开或激光切割技术，模制阵列封装组件40被分隔为上述的可能的单个封装件。一旦分隔，封装件41、42、410和420具有经分割的密封层66，其是相对于腔体模制层已经被物理剪断的密封层。
图13示出了根据本发明的模制阵列封装、模制结构、扁平封装结构或封装组件400的截面图。封装组件400与封装组件40类似，除了细长的标志或管芯附着叶片510不具有带通孔的水平露出的翼片之外，因为密封层660覆盖了细长的标志510的上表面511。在可选的实施例中，形成具有槽口或沟槽661的密封层660，其在沿线670分隔后，提供用于固定或安装夹片类型的热沉的结构。沿线670分隔之后，提供垂直且露出的翼片部分512，其与标志部分510露出的基本上垂直面对应。
图14是根据本发明的再另一个实施例的模制阵列封装、模制结构、扁平封装结构或封装组件401的截面图。封装组件401与封装组件400类似，除了密封层660没有覆盖所有的上表面511而留下水平且露出的翼片部分612以外。翼片部分612不包括通孔，并且提供常规的方式将该封装夹在下级组件上。
图15示出了根据本发明在制造的中间阶段时组件结构或副组件710的部分顶视图。结构710与图5中所示的结构71类似，除了提供不具有通孔的细长的标志或标志部分510(图5中的类似结构51)以外。线670被示出为垂直的分隔线，作为在使用与图6-7相结合的上面提到的工艺类似的工艺密封组件结构710之后，切穿细长的标志部分510时位置的例子。
图16示出了根据本发明的具有通过导电引线157直接与第二模制器件部分152相连的分隔的模制第一器件或功率器件部分151的集成多芯片模制阵列封装150。模制功率器件部分151包括与在图9或11所示的封装41和410类似的单个的或多芯片封装，并包括具有通孔53的翼片部分52。第二模制器件部分152包括，例如，模制阵列封装逻辑、传感器、存储器、光学电路器件或其组合，并且通过在该两部分之间延伸的露出或柔韧的导电引线157被连接到功率器件部分151。在这个实施例中，第二模制器件部分152还包括用于与下级组件耦接或连接的无引线连接部分。这种连接部分的例子如图4中的部分57a所示。
图17示出了根据本发明的另一个实施例的具有通过导电引线157直接与第二模制器件部分153连接的分隔的模制第一器件或功率器件部分151的集成多芯片模制阵列封装160的顶视图。封装160与封装150类似，除了第二模制器件部分153还包括用于连接或耦接下级组件的外部的露出或向外延伸的导电引线158。导电引线158可以代替无引线连接部分(例如图4中所示的57a)使用或附加使用。
根据本发明的封装150和160提供了柔韧的或可弯曲的三维阵列，与用于功率器件部分151的各种热沉技术相兼容。例如，图18示出了根据本发明的附着于下级组件162的封装150的侧面图。在这个实施例中，弯曲或定型引线157，使热沉器件163位于功率器件部分151和组件162之间，这提供了更加有效的冷却功率器件部分151的方法。具有通孔53的翼片部分52提供了用于将功率器件部分151连接至热沉器件163的附着手段。举例来说，为此目的使用插脚、夹子、螺钉154等。
图19示出了根据本发明的附着于下级组件167的封装160的侧面图。在这个实施例中，弯曲或定型引线157，以将功率器件151设置在邻接垂直热沉结构或室171的位置。使用例如插脚、夹子、螺钉154等将功率器件部分151附着于结构171。
图20示出了根据本发明在制造的中间步骤中，用于制造图16和17的封装的组件结构或副组件710的部分顶视图。所示的布局例子与方块扁平封装组件技术相兼容。结构710包括阵列引线框架或主引线框架720。举例来说，主引线框架720包括如下单个的标准化学碾压或压印的片材料：铜合金(例如TOMAC4、TAMAC5、2ZFROFC或CDA194)、镀铜的铁/镍合金(例如镀铜合金42)、镀覆的铝、镀覆的塑料等。镀覆材料包括铜、银或多层镀覆这种镍-钯和金。
主引线框架720包括阵列标志部分或多个标志或细长的标志部分751。第一半导体器件759附着于标志部分751，而且还使用例如导线键合763或导电夹片(没有示出)连接或耦接至多条引线157。
使用焊料附着层、导电环氧树脂等或使用绝缘层将第一半导体器件759附着于标志部分751，如结合图5描述的工艺适合这种附着步骤。
举例来说，器件759包括功率MOSFET、绝缘栅双极型晶体管、双极型晶体管、晶闸管、二极管等。细长的标志部分751还包括具有通孔753的标志部分752。在替代的实施例中，提供在图20的顶部所示的没有通孔753的翼片部分752，以提供给夹片安装技术。
主引线框架720还包括阵列多芯片引线框架721或多个多芯片引线框架721，包括多个标志723和导电引线158。使用绝缘的或导电的附着层将电子器件859和959附着于标志723，同时使用如导线键合的连接结构将器件859和959连接至导电引线157和158。举例来说，器件859和959包括传感器、光学、逻辑、控制或存储器件、其组合等。诸如电容元件的元件1059可以用在邻近的导电引线之间以提供对例如静电放电事件的电路保护。
图21示出了根据本发明的在下一步工艺中的组件结构710的顶视图。在这步骤中，将组件结构710设置在如转移模制装置的模制设备中。将固态树脂片放置在精选装置(cull)或坩锅783中。根据本发明，当加热坩锅783来融化固态树脂片，迫使液化的树脂材料从坩锅783穿过流道786流到狭缝模制腔中以形成密封层766，同时让引线157和158的一部分和具有通孔753的翼片部分752露出。应当理解，在一个实施例中，翼片751和/或723的下表面和引线158的下表面没有密封。
图22示出了根据本发明在分隔之前的具有包含通孔753的翼片752的集成多芯片模制阵列封装结构810的顶视图。分割线803、804、806和807代表用于将结构810分隔为单独的多芯片模制阵列封装的例子。线803是用于分隔单个的封装和穿透器件的模制部分的水平或第一方向的切割线。线804是用于从主引线框架分隔翼片部分752的垂直或第二方向的切割线。可选的切割线806是根据本发明提供诸如如图16所示的不含引线或无引线实施例的垂直或第二方向的切割线。
可选的切割线807是根据本发明实施例提供诸如如图17所示的含引线的实施例的垂直或第二方向的切割线。
因此，很明显，根据本发明，已经提供了一种用于形成具有包含通孔的露出的翼片的结构和方法。该封装和方法提供了可选的实施例灵活性，包括：无引线器件、含引线器件和包括具有包含引线互连的多模制部分的器件的多芯片器件。
尽管参考其特定的实施例已经描述和说明了本发明，但是并不局限于说明的实施例。例如，根据本发明的器件的露出引线根据组装需要而可以是平整的、或且是以不同的角度弯曲或成形的形状(例如，鸥形翼的形状)。

Claims (10)

1.一种制作模制阵列封装器件的方法，包括以下步骤：
提供具有包含翼片部分的多个标志和与该多个标志隔开的多条引线的主引线框架；
将电子芯片安装于该标志部分；
耦接该电子芯片至该多条引线；
密封该主引线框架，同时让所述多条引线的一部分露出以提供模制阵列封装组件；和
将该模制阵列封装组件分隔开为单独的模制封装器件。
2.权利要求1的方法，其中所述提供主引线框架的步骤包括提供没有坝条并具有多个细长的标志部分的主引线框架；并且
其中所述安装步骤包括在每个细长的标志部分上安装至少两个电子芯片；并且
其中所述分隔步骤包括通过每个细长的标志部分分隔。
3.权利要求2的方法，其中所述提供主引线框架的步骤包括提供具有穿过翼片部分而延伸的通孔的主引线框架，并且
其中所述密封步骤包括密封该主引线框架同时还让该通孔露出。
4.权利要求1的方法，其中所述分隔步骤包括分隔以形成具有露出的引线的模制阵列封装，从该模制阵列封装的模制部分延伸出引线。
5.权利要求1的方法，其中所述分隔步骤包括分隔以制作无引线模制阵列封装。
6.权利要求1的方法，其中所述分隔步骤包括穿过所述多个标志部分切割。
7.一种制作扁平封装结构的工艺，包括以下步骤：
提供具有包含翼片的多个细长的标志和多条引线的阵列引线框架；
将电子芯片附着于该细长的标志部分；
耦接该电子芯片至所述多条引线；
在该细长的标志部分的一部分上形成连续的密封层，同时让该翼片和所述多条引线的一部分露出以提供模制组件；和
通过穿过所述多个细长的标志部分、穿过该连续的密封层、并且穿过所述多条引线进行分隔，将该模制组件分割成单独的封装件，从而提供具有露出的翼片部分的扁平封装结构。
8.一种多芯片扁平封装器件，包括：
具有翼片部分的第一标志；
附着于该第一标志的第一电子芯片；
与该第一标志隔开的第一多条引线，其中所述第一电子芯片耦接至该导电引线；
与该第一多条引线隔开的第二标志；
与该第二管芯附着叶片隔开的第二多条导电引线；
附着于该第二管芯附着叶片并且耦接至第一和第二多条导电引线的第二电子芯片；
覆盖该第一标志、该第一电子芯片和第一导电引线的一部分从而形成第一扁平封装器件的第一密封层；和
覆盖该第二标志、该第二电子芯片和第一导电引线的其它部分从而形成第二扁平封装器件的第二密封层，其中所述第一导电引线的剩余部分在第一和第二扁平封装器件之间露出，并且其中第一导电引线中的至少一条将第一和第二扁平封装器件连接起来。
9.权利要求8的多芯片封装器件，其中所述翼片部分为附着于下级组件而露出。
10.一种扁平封装半导体器件，包括：
具有翼片部分的标志；
基本上与43共面并且与标志部分隔开的导电引线；
耦接至该标志和该导电引线的半导体器件；以及
覆盖该标志和半导体器件的经分割的密封层，其中所述翼片部分露出。
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