CN1922737B - 具有不对称电荷陷获的多态存储器单元 - Google Patents

具有不对称电荷陷获的多态存储器单元 Download PDF

Info

Publication number
CN1922737B
CN1922737B CN2005800056006A CN200580005600A CN1922737B CN 1922737 B CN1922737 B CN 1922737B CN 2005800056006 A CN2005800056006 A CN 2005800056006A CN 200580005600 A CN200580005600 A CN 200580005600A CN 1922737 B CN1922737 B CN 1922737B
Authority
CN
China
Prior art keywords
voltage
grid
trapping layer
drain
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2005800056006A
Other languages
English (en)
Other versions
CN1922737A (zh
Inventor
K·普劳尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN1922737A publication Critical patent/CN1922737A/zh
Application granted granted Critical
Publication of CN1922737B publication Critical patent/CN1922737B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

一种多态NAND存储器单元由基片中的两个漏极/源极区构成。在漏极/源极区之间所述基片之上形成氧化物-氮化物-氧化物结构。氮化物层用作不对称电荷陷获层。控制和栅极位于该氧化物-氮化物-氧化物结构上。漏极/源极区上的不对称偏压使得漏极/源极区具有更高的电压以通过栅极感应漏极泄漏注入至基本邻近于漏极/源极区的陷获层而注入不对称分布空穴。

Description

具有不对称电荷陷获的多态存储器单元
技术领域
本发明一般涉及存储器单元，尤其涉及多态非易失性存储器单元。
背景技术
存储器装置现具有各种样式和大小。一些存储器装置在性质上是易失性的且在没有有源电源的情况下不能保存数据。通常的易失性存储器是包括作为电容器形成的存储器单元的DRAM。电容器上的电荷或没有电荷指示存储器单元中存储的数据的二进制状态。动态存储器装置与非易失性存储器相比需要更多的努力来保持数据，但通常前者更快地进行读写。
非易失性存储器装置可具有不同配置。例如，浮置栅极存储器装置是非易失性存储器，它使用浮置栅极晶体管来存储数据。通过改变晶体管的阈值电压将数据写入存储器单元并在断电时保持该数据。可以擦除晶体管以恢复晶体管的阈值电压。存储器可在擦除块中排列，其中擦除块中的所有存储器单元可被一次擦除。这些非易失性存储器装置通常称作闪存。
闪存可使用浮置栅极技术或陷获技术。浮置栅极单元包括横向隔开的源极和漏极区，以形成一中间沟道区。源极和漏极区形成于硅基片的共用水平面中。通常由掺杂多晶硅制成的浮置栅极设置于沟道区上并通过氧化物与其它单元元件电隔离。浮置栅极技术的非易失性存储器功能通过隔离的浮置栅极上存储的电荷存在与否来创建。陷获技术通过用于俘获并存储电子或空穴的隔离陷阱中存储的电荷存在与否而用作非易失性存储器。
为使存储器制造商保持竞争性，存储器设计者不断尝试增加闪存装置的密度。增加闪存装置的密度一般需要减小存储器单元之间的间隔和/或使存储器单元更小。许多装置元件的尺寸越小会引起单元的操作问题。例如，源极/漏极区之间的沟道变得更短，可能引起严重的短沟道效应。此外，在较小的单元尺寸的情况下，从单元的一个边角到另一个边角的可能的电荷迁移变得更加重要。
出于上述原因以及以下本领域的熟练技术人员通过阅读和理解本说明书而变得显而易见的原因，本领域需要更高密度的存储器装置。
发明内容
本发明涉及关于存储器密度的上述问题和其它问题，且这些问题将通过阅读和学习以下说明书加以理解。
本发明包括多态NAND存储器结构。该结构包括第一导电材料的基片。第一和第二有源区形成于该基片内。第一和第二有源区由第二导电材料构成。在一个实施例中，第一导电材料是p型材料且第二导电材料是n型材料。
控制栅极位于第一和第二有源区之上和它们之间.陷获层位于控制栅极和基片之间.陷获层通过第一介电层与控制栅极隔离并通过第二介电层与基片隔离.陷获层能响应于第一和第二有源区的不对称偏压进行不对称电荷陷获.这允许存储邻近于第一有源区的第一数据位和邻近于第二有源区的第二数据位.
本发明的其它实施例包括改变范围的方法和装置。
附图说明
图1示出了用于编程本发明的具有不对称电荷陷获的多态NAND存储器单元的一个实施例的剖视图。
图2示出了用于编程本发明的具有不对称电荷陷获的多态NAND存储器单元的另一个实施例的剖视图。
图3示出了用于擦除本发明的具有不对称电荷陷获的多态NAND存储器单元的实施例的剖视图。
图4示出了本发明的具有不对称电荷陷获的多态NAND存储器单元的另一实施例的剖视图。
图5示出了用于读取本发明的具有不对称电荷陷获的多态NAND存储器单元的实施例的剖视图。
图6示出了本发明的多态NAND存储器单元阵列的一部分。
图7示出了用于图6实施例的操作的电压的表格。
图8示出了本发明的电子系统的一个实施例的框图。
具体实施方式
在本发明的以下详细描述中，参考构成其一部分的附图，其中为说明示出了可以实施本发明的具体实施例。图中，相同的标号贯穿若干示图描述基本相似的组件。这些实施例充分详细地加以描述以使本领域的熟练技术人员能实施本发明。可以使用其它实施例，且可进行结构、逻辑和电气改变而不背离本发明的范围。以下描述中使用的术语晶片或基片包括任何基底半导体结构。这两者可理解为包括蓝宝石衬底硅(SOS)技术、绝缘衬底硅(SOI)技术、薄膜晶体管(TFT)技术、掺杂和未掺杂半导体、基底半导体结构支持的硅的外延层以及本领域熟练技术人员公知的其它半导体结构。此外，当参考以下描述中的晶片或基片时，以前的工艺步骤可加以应用以形成基底半导体结构中的区域/结，且术语晶片或基片包括包含这些区域/结的底部层。因此，以下的详细描述不被认为是限制性的，且本发明的范围仅通过所附权利要求书及其等效技术方案所限定。
浮置栅极存储器上的电荷形成浮置栅极上展开的高斯表面。本发明的基于陷获的存储器中的电荷被局部化且不展开。该属性允许不对称电荷以及形成多态单元的能力。
图1示出了用于编程具有不对称电荷陷获的多态NAND存储器单元的一个实施例的剖视图。该实施例由具有两个有源区105和107的基片101构成。每一区域105和107交替用作漏极或源极区，这取决于所执行的操作和所施加的电压。
在一个实施例中，漏极和源极区105和107是n型导电材料而基片101是p型导电材料。在可选实施例中，这些导电材料类型是可改换的。
在漏极/源极区105和107之间的沟道上是氧化物-氮化物-氧化物(ONO)结构103、109和111.氮化物层103通过第一氧化物层111与基片隔离并通过第二氧化物层109与控制栅极100隔离.氮化物层103是存储本发明的不对称电荷的陷获层.本发明不限于任何特定数量的介电和/或陷获层.
本发明也不限于介电/陷获层的组成。在一个实施例中，氧化物材料可以是氧化铝。陷获层可以是硅纳米晶体材料。可选实施例使用其它类型的介电材料和/或其它陷获层材料。
图1的实施例示出了陷获层103的左侧中的一个数据位的编程。这是通过将相对较高的负电压施加到控制栅极100来完成的。该电压截断沟道，以防止从漏极区105到源极区107的泄漏。在一个实施例中，栅极电压在-10V到-15V之间。可选实施例可使用其它栅极电压范围。
将不对称偏压施加到漏极区105和源极区107。在一个实施例中，正5V施加于漏极区105且源极区107被接地(即，0V)。来自栅极100和结场两者的结左侧上的高电位使得栅极感生漏极泄漏(GIDL)条件，它将空穴注入该左结附近的陷获层103。注入的空穴与来自先前擦除条件的电子中和，从而使得阈值电压降低。
右结具有降低的电场，因为结偏压为零。这导致不注入空穴的偏置条件。沟道右侧上的电子不由空穴补偿，从而使得初始的编程或擦除条件得以保留。
图2示出了用于编程具有不对称电荷陷获的多态NAND存储器单元的第二实施例的剖视图。图2的实施例示出了陷获层103的右侧中一个数据位的编程。这是通过将相对较高的负电压施加到控制栅极100上来完成的。该电压截断沟道以防止从漏极区107到源极区105的泄漏。在一个实施例中，栅极电压在-10V到-15V之间。可选实施例可使用其它栅极电压范围。
将不对称偏压施加于漏极区107和源极区105。在一个实施例中，将正5V施加于漏极区107且源极区105接地(即，0V)。来自栅极100和结场两者的结右侧上的高电位引起将空穴注入右结附近的陷获层103的GIDL条件。注入的空穴与来自先前擦除条件的电子中和，从而使得阈值电压降低。
左结具有降低的场，因为结偏压为零。这导致了不注入空穴的偏置条件。沟道左侧上的电子不由空穴补偿，从而使得上述编程条件得以保留。
图3示出了用于擦除具有不对称电荷陷获的多态NAND存储器单元的实施例的剖视图。擦除操作通过将电子从倒置区301中的均匀电荷薄层隧穿入陷获层303而执行。这通过陷获层103中的连续均匀陷获电荷薄层形成了高阈值电平。在一个实施例中，通过施加范围10-20V的正栅极电压来实现擦除操作。漏极和源极区两者被接地(即，0V)。可选实施例可使用其它电压和电压范围。
图4示出了具有不对称电荷陷获的多态NAND存储器单元的另一实施例的剖视图。本实施例通过将控制栅极扩展入陷获层403而形成了不连续的陷获层403。这获得的更好的传感、更好的数据保持和抗二次发射。
图5示出了使用源极/漏极区的不对称偏置来读取本发明的多态NAND存储器单元的左侧的方法。左数据位500可通过将相对较高的偏压施加到单元的由源极/漏极区501而被读取。在一个实施例中，该漏极电压的范围为1-3V。用作源极的左漏极/源极区503接地，且VG是范围3-6V的正电压。可选实施例可使用其它电压和电压范围。
右数据位502使用逆向过程被读取。在该实施例中，左漏极/源极区503接地，而右源极/漏极区501被施加了相对较高的电压(例如，1-3V)。该读取实施例中的VG也在3-6V范围内.可选实施例可使用其它电压和电压范围.
图6示出了本发明的多态NAND存储器单元的两个字符串阵列。图7示出了用于该存储器阵列的选定列的不同操作模式的电压的表格。
图6的NAND存储器阵列的一部分由如上所述的多态NAND存储器单元的两个列601和602构成。选择一个列601的同时不选择第二个列602。选定的列601由用于漏极电压Vd的选择栅极605和用于源极电压Vs的选择栅极606构成。选定的列601也由分别与控制栅极电压VWL1-VWL3相连接的三个多态NAND存储器单元610-612构成。图6的列仅用于说明目的，因为真实的存储器列由基本上更大量的单元构成。
参考图7的电压表，示出了两个版本的擦除操作。在一个选项中，如上所述，漏极和源极电压Vd和Vs是0V且控制栅极电压VH在10-20V范围内。在该实施例中，选择栅极605和606的控制栅极连接到VH/2。其它擦除操作实施例可使用同时来自阵列两侧的GIDL空穴注入。
擦除操作的第二选项保留漏极和源极连接浮置为开连接(O/C)。在该实施例中，选择栅极605和606也浮置。
在中间单元611中的左位的编程操作期间，VWL2是-VH(例如，-10到-20V)、Vd是VDP(例如，3-6V)且VS连接到接地。选择栅极605和606的控制栅极连接到VX1且列601中的其它单元610和612的控制栅极连接到VX2。在一个实施例中，VX1约等于VX2，VX2约等于VDP+VT。如本领域已知的，VT是单元的阈值电压。在VS连接到VDP且Vd连接到接地的情况下，中间单元611的右位的编程操作使用与左位基本相同的电压。可选实施例使用其它实施例来实现基本类似的结果。
在中间单元611中的左位的读操作期间，VWL2是VR(例如，3-6V)、VD是VDR，且VS连接到接地。选择栅极605和606的控制栅极连接到VY1且列601中的其它单元610和612的控制栅极连接到VY2。在一个实施例中，VY1约等于VY2，VY2约等于VDR+VT，其中VDR的范围是4-6V。在VS连接到接地且Vd连接到VDR的情况中，中间单元611中右位的读操作使用与左位基本相同的电压。可选实施例使用其它实施例来实现基本类似的结果。
图8示出了可结合本发明的多态NAND存储器单元的存储器装置800的功能框图。存储器装置800耦合到处理器810。处理器810可以是微处理器或者某些其它类型的控制电路。存储器装置800和处理器810形成了电子系统820的一部分。存储器装置800被简化以关注对理解本发明有帮助的存储器的特点。
存储器装置包括存储器单元830的阵列。在一个实施例中，存储器单元是非易失性浮置栅极存储器单元且存储器阵列830排列于行和列的存储体中。
提供地址缓冲电路840以锁存地址输入连接A0-Ax842上提供的地址信号。地址信号由行解码器844和列解码器846接收并解码，以访问存储器阵列830。本领域的熟练技术人员得益于本说明书可以理解，地址输入连接的数量取决于存储器阵列830的密度和架构。即，地址数量随着存储器单元计数的增加以及存储体和块计数的增加两者而增加。
存储器装置800通过用传感/缓冲电路850检测存储器阵列列中的电压或电流变化来读取存储器阵列830中的数据。在一个实施例中，传感/缓冲电路被耦合以便从存储器阵列830中读取并锁存数据行。数据输入和输出缓冲电路860被包括用于多个数据连接862上与控制器810的双向数据通信。写入电路855被提供用于将数据写到存储器阵列。
控制电路870解码来自处理器810的控制连接872上提供的信号。这些信号被用于控制存储器阵列830上的操作，包括数据读取、数据写入和擦除操作。控制电路870可以是状态机、序列发生器或某些其它类型的控制器。
图8所示的闪存装置已被简化，以便于存储器特点的基本理解。闪存的内部电路和功能的更详细理解是本领域熟练技术人员已知的。
结论
总之，本发明的多态NAND单元是基于陷获的存储器，它允许存储不对称电荷，从而提供了两个数据位的存储。由于陷获功能，该存储器单元提供了高存储器密度、低功率操作和改进的可靠性。
尽管这里示出并描述了具体实施例，但本领域的普通技术人员可以理解的是为实现相同目的计算出的任何排列可替代所示的具体实施例。本发明的许多适应方案是本领域的普通技术人员显而易见的。因此，本申请旨在覆盖本发明的任何适应方案或变型。显然，本发明仅仅由所附权利要求书及其等效技术方案所限定。

Claims (13)

1.一种存储器装置，包括：
存储器阵列，所述存储器阵列包括以列排列的多个多态NAND存储器单元，每个单元包括漏极区，源极区，控制栅极和氮化物陷获层，所述陷获层适应于响应于所述漏极区和所述源极区的不对称偏压而进行邻近于所述漏极区的第一数据位和邻近于所述源极区的第二数据位的不对称电荷陷获；
多个选择栅极，第一选择栅极在所述列的一端，而第二选择栅极在所述列的另一端，其中在所述多个多态NAND存储器单元的一多态NAND存储器单元的编程操作期间，通过所述第一选择栅极来施加漏极电压，并通过所述第二选择栅极来施加源极电压，所述漏极和源极电压基于所述第一和第二数据位是否正在被编程而具有不同的电位；以及
控制电路，其中所述控制电路被配置成控制所述多态NAND存储器单元的偏压，且所述控制电路还被配置成在所述存储器单元的编程操作期间向所述多态NAND存储器单元的控制栅极施加-20V电压。
2.如权利要求1所述的存储器装置，其特征在于，所述控制电路还被配置成偏压所述存储器单元，其中当对所述第一数据位编程时，所述源极电压大致等于0V而所述漏极电压大致等于5V，而当对所述第二数据位编程时，所述漏极电压大致等于0V而所述源极电压大致等于5V。
3.如权利要求1所述的存储器装置，其特征在于，在形成所述氮化物陷获层的基片上形成所述漏极区和所述源极区。
4.如权利要求3所述的存储器装置，其特征在于，在所述基片和所述氮化物陷获层之间形成第一介电层。
5.如权利要求4所述的存储器装置，其特征在于，在所述氮化物陷获层和所述控制栅极之间形成第二介电层。
6.如权利要求5所述的存储器装置，其特征在于，所述第一介电层和所述第二介电层由氧化铝构成。
7.一种存储器系统，包括：
控制所述系统操作的处理器；
包括多个存储器单元的NAND非易失存储设备，每个存储单元包含：
包括第一导电材料的基片；
所述基片内的第一和第二有源区，所述第一和第二有源区由第二导电材料构成；
所述第一和第二有源区之上和之间的控制栅极；以及
所述控制栅极和所述基片之间的陷获层，所述陷获层适应于响应于所述第一和第二有源区的不对称偏压而进行邻近于所述第一有源区的第一数据位和邻近所述第二有源区的第二数据位的不对称电荷陷获；以及
其中所述存储设备还包括控制电路，所述控制电路被配置成控制每个存储器单元的偏压，且所述控制电路还被配置成在所述存储器单元的第一和第二有源区的不对称偏压期间，将存储器单元的控制栅极偏压到-10到-20V的电压。
8.如权利要求7所述的系统，其特征在于，所述陷获层适应于通过栅极感应漏极泄漏空穴注入进行编程。
9.如权利要求7所述的系统，其特征在于，所述陷获层适应于通过电子注入进行擦除。
10.如权利要求7所述的系统，其特征在于，还包括将所述陷获层与所述基片和所述控制栅极进行隔离的多个介电层。
11.如权利要求7所述的系统，其特征在于，所述陷获层是通过所述控制栅极的延伸被分开的不连续陷获层。
12.如权利要求7所述的系统，其特征在于，所述第一导电材料包括p型导电材料。
13.如权利要求7所述的系统，其特征在于，所述第二导电材料包括n型导电材料。
CN2005800056006A 2004-02-24 2005-02-15 具有不对称电荷陷获的多态存储器单元 Active CN1922737B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/785,785 US7072217B2 (en) 2004-02-24 2004-02-24 Multi-state memory cell with asymmetric charge trapping
US10/785,785 2004-02-24
PCT/US2005/004765 WO2005083797A1 (en) 2004-02-24 2005-02-15 Multi-state memory cell with asymmetric charge trapping

Publications (2)

Publication Number Publication Date
CN1922737A CN1922737A (zh) 2007-02-28
CN1922737B true CN1922737B (zh) 2010-05-05

Family

ID=34861685

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2005800056006A Active CN1922737B (zh) 2004-02-24 2005-02-15 具有不对称电荷陷获的多态存储器单元

Country Status (7)

Country Link
US (4) US7072217B2 (zh)
EP (2) EP2416367A3 (zh)
JP (2) JP4866835B2 (zh)
KR (1) KR100852849B1 (zh)
CN (1) CN1922737B (zh)
TW (1) TWI267990B (zh)
WO (1) WO2005083797A1 (zh)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804502B2 (en) 2001-10-10 2004-10-12 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
EP1774620B1 (en) 2004-06-23 2014-10-01 Peregrine Semiconductor Corporation Integrated rf front end
US7307888B2 (en) * 2004-09-09 2007-12-11 Macronix International Co., Ltd. Method and apparatus for operating nonvolatile memory in a parallel arrangement
US7170785B2 (en) * 2004-09-09 2007-01-30 Macronix International Co., Ltd. Method and apparatus for operating a string of charge trapping memory cells
US7247907B2 (en) * 2005-05-20 2007-07-24 Silicon Storage Technology, Inc. Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US7485526B2 (en) * 2005-06-17 2009-02-03 Micron Technology, Inc. Floating-gate structure with dielectric component
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7910993B2 (en) 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US7489546B2 (en) 2005-12-20 2009-02-10 Micron Technology, Inc. NAND architecture memory devices and operation
US7450422B2 (en) * 2006-05-11 2008-11-11 Micron Technology, Inc. NAND architecture memory devices and operation
US7525841B2 (en) * 2006-06-14 2009-04-28 Micron Technology, Inc. Programming method for NAND flash
US7551467B2 (en) * 2006-08-04 2009-06-23 Micron Technology, Inc. Memory device architectures and operation
JP2008166528A (ja) * 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US7898863B2 (en) * 2007-08-01 2011-03-01 Micron Technology, Inc. Method, apparatus, and system for improved read operation in memory
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
EP3346611B1 (en) 2008-02-28 2021-09-22 pSemi Corporation Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device
US8643079B2 (en) * 2008-05-05 2014-02-04 Micron Technology, Inc. Nanocrystal formation using atomic layer deposition and resulting apparatus
US7692972B1 (en) 2008-07-22 2010-04-06 Actel Corporation Split gate memory cell for programmable circuit device
KR101569894B1 (ko) * 2008-11-12 2015-11-17 삼성전자주식회사 불 휘발성 메모리 장치의 프로그램 방법
JP5275052B2 (ja) * 2009-01-08 2013-08-28 株式会社東芝 不揮発性半導体記憶装置
US8723260B1 (en) 2009-03-12 2014-05-13 Rf Micro Devices, Inc. Semiconductor radio frequency switch with body contact
US9318336B2 (en) 2011-10-27 2016-04-19 Globalfoundries U.S. 2 Llc Non-volatile memory structure employing high-k gate dielectric and metal gate
US8829967B2 (en) 2012-06-27 2014-09-09 Triquint Semiconductor, Inc. Body-contacted partially depleted silicon on insulator transistor
US8729952B2 (en) 2012-08-16 2014-05-20 Triquint Semiconductor, Inc. Switching device with non-negative biasing
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US8847672B2 (en) 2013-01-15 2014-09-30 Triquint Semiconductor, Inc. Switching device with resistive divider
US9214932B2 (en) 2013-02-11 2015-12-15 Triquint Semiconductor, Inc. Body-biased switching device
US8977217B1 (en) 2013-02-20 2015-03-10 Triquint Semiconductor, Inc. Switching device with negative bias circuit
US8923782B1 (en) 2013-02-20 2014-12-30 Triquint Semiconductor, Inc. Switching device with diode-biased field-effect transistor (FET)
US9203396B1 (en) 2013-02-22 2015-12-01 Triquint Semiconductor, Inc. Radio frequency switch device with source-follower
US20150236798A1 (en) 2013-03-14 2015-08-20 Peregrine Semiconductor Corporation Methods for Increasing RF Throughput Via Usage of Tunable Filters
US9406695B2 (en) 2013-11-20 2016-08-02 Peregrine Semiconductor Corporation Circuit and method for improving ESD tolerance and switching speed
US9379698B2 (en) 2014-02-04 2016-06-28 Triquint Semiconductor, Inc. Field effect transistor switching circuit
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
WO2016154144A1 (en) * 2015-03-21 2016-09-29 NEO Semiconductor, Inc. Sonos byte-erasable eeprom
US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US11211399B2 (en) 2019-08-15 2021-12-28 Micron Technology, Inc. Electronic apparatus with an oxide-only tunneling structure by a select gate tier, and related methods
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch
WO2021246825A1 (ko) * 2020-06-05 2021-12-09 한양대학교 산학협력단 강유전체 물질 기반의 3차원 플래시 메모리 및 그 동작 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330930A (en) * 1980-02-12 1982-05-25 General Instrument Corp. Electrically alterable read only memory semiconductor device made by low pressure chemical vapor deposition process
US5021999A (en) * 1987-12-17 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device with facility of storing tri-level data
US6288943B1 (en) * 2000-07-12 2001-09-11 Taiwan Semiconductor Manufacturing Corporation Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate
US20030062567A1 (en) * 2001-09-28 2003-04-03 Wei Zheng Non volatile dielectric memory cell structure with high dielectric constant capacitive coupling layer
WO2003038907A1 (en) * 2001-10-31 2003-05-08 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
EP1324380A2 (en) * 2001-12-20 2003-07-02 Saifun Semiconductors Ltd Non-volatile memory device and method of fabrication
US20030193062A1 (en) * 2002-04-16 2003-10-16 Fuh-Cheng Jong Nonvolatile memory cell for prevention from second bit effect

Family Cites Families (114)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US622768A (en) * 1899-04-11 hellwig
US649877A (en) * 1899-11-22 1900-05-15 William G Shedd Measure for liquid gold.
US4184207A (en) * 1978-01-27 1980-01-15 Texas Instruments Incorporated High density floating gate electrically programmable ROM
US4420504A (en) * 1980-12-22 1983-12-13 Raytheon Company Programmable read only memory
JPS61150369A (ja) * 1984-12-25 1986-07-09 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
US4881114A (en) * 1986-05-16 1989-11-14 Actel Corporation Selectively formable vertical diode circuit element
US5241496A (en) * 1991-08-19 1993-08-31 Micron Technology, Inc. Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells
US5357462A (en) * 1991-09-24 1994-10-18 Kabushiki Kaisha Toshiba Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller
US5467305A (en) * 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5379253A (en) * 1992-06-01 1995-01-03 National Semiconductor Corporation High density EEPROM cell array with novel programming scheme and method of manufacture
US5330930A (en) * 1992-12-31 1994-07-19 Chartered Semiconductor Manufacturing Pte Ltd. Formation of vertical polysilicon resistor having a nitride sidewall for small static RAM cell
US5378647A (en) * 1993-10-25 1995-01-03 United Microelectronics Corporation Method of making a bottom gate mask ROM device
US5397725A (en) * 1993-10-28 1995-03-14 National Semiconductor Corporation Method of controlling oxide thinning in an EPROM or flash memory array
US5429967A (en) * 1994-04-08 1995-07-04 United Microelectronics Corporation Process for producing a very high density mask ROM
US5576236A (en) * 1995-06-28 1996-11-19 United Microelectronics Corporation Process for coding and code marking read-only memory
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
JP3191693B2 (ja) * 1996-08-29 2001-07-23 日本電気株式会社 半導体記憶装置の製造方法
US6028342A (en) * 1996-11-22 2000-02-22 United Microelectronics Corp. ROM diode and a method of making the same
US6097059A (en) * 1996-12-27 2000-08-01 Sanyo Electric Co., Ltd. Transistor, transistor array, method for manufacturing transistor array, and nonvolatile semiconductor memory
US5792697A (en) * 1997-01-07 1998-08-11 United Microelectronics Corporation Method for fabricating a multi-stage ROM
TW319904B (en) * 1997-01-20 1997-11-11 United Microelectronics Corp Three dimensional read only memory and manufacturing method thereof
US5801401A (en) * 1997-01-29 1998-09-01 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
TW347581B (en) * 1997-02-05 1998-12-11 United Microelectronics Corp Process for fabricating read-only memory cells
US6190966B1 (en) * 1997-03-25 2001-02-20 Vantis Corporation Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US6297096B1 (en) * 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
IL125604A (en) * 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
TW406378B (en) * 1998-02-03 2000-09-21 Taiwan Semiconductor Mfg The structure of read-only memory (ROM) and its manufacture method
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
US6215148B1 (en) * 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6348711B1 (en) * 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US6133102A (en) * 1998-06-19 2000-10-17 Wu; Shye-Lin Method of fabricating double poly-gate high density multi-state flat mask ROM cells
KR100331545B1 (ko) * 1998-07-22 2002-04-06 윤종용 다단계 화학 기상 증착 방법에 의한 다층 질화티타늄막 형성방법및 이를 이용한 반도체 소자의 제조방법
TW380318B (en) 1998-07-29 2000-01-21 United Semiconductor Corp Manufacturing method for flash erasable programmable ROM
US6251731B1 (en) * 1998-08-10 2001-06-26 Acer Semiconductor Manufacturing, Inc. Method for fabricating high-density and high-speed nand-type mask roms
US6184089B1 (en) * 1999-01-27 2001-02-06 United Microelectronics Corp. Method of fabricating one-time programmable read only memory
US6256231B1 (en) * 1999-02-04 2001-07-03 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells and method of implementing same
US6157570A (en) 1999-02-04 2000-12-05 Tower Semiconductor Ltd. Program/erase endurance of EEPROM memory cells
US6081456A (en) * 1999-02-04 2000-06-27 Tower Semiconductor Ltd. Bit line control circuit for a memory array using 2-bit non-volatile memory cells
US6134156A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays
US6147904A (en) * 1999-02-04 2000-11-14 Tower Semiconductor Ltd. Redundancy method and structure for 2-bit non-volatile memory cells
US6181597B1 (en) * 1999-02-04 2001-01-30 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells with serial read operations
US6108240A (en) * 1999-02-04 2000-08-22 Tower Semiconductor Ltd. Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions
US6487050B1 (en) * 1999-02-22 2002-11-26 Seagate Technology Llc Disc drive with wear-resistant ramp coating of carbon nitride or metal nitride
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6174758B1 (en) * 1999-03-03 2001-01-16 Tower Semiconductor Ltd. Semiconductor chip having fieldless array with salicide gates and methods for making same
US6208557B1 (en) 1999-05-21 2001-03-27 National Semiconductor Corporation EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming
JP2000334976A (ja) * 1999-05-31 2000-12-05 Canon Inc インクジェット記録装置、インク供給装置、およびインク供給方法
US6218695B1 (en) * 1999-06-28 2001-04-17 Tower Semiconductor Ltd. Area efficient column select circuitry for 2-bit non-volatile memory cells
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6204529B1 (en) * 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
US6303436B1 (en) * 1999-09-21 2001-10-16 Mosel Vitelic, Inc. Method for fabricating a type of trench mask ROM cell
FR2799570B1 (fr) * 1999-10-08 2001-11-16 Itt Mfg Enterprises Inc Commutateur electrique perfectionne a effet tactile a plusieurs voies et a organe de declenchement unique
US6240020B1 (en) * 1999-10-25 2001-05-29 Advanced Micro Devices Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices
US6175523B1 (en) * 1999-10-25 2001-01-16 Advanced Micro Devices, Inc Precharging mechanism and method for NAND-based flash memory devices
US6429063B1 (en) * 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
JP4923318B2 (ja) * 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
US6291854B1 (en) * 1999-12-30 2001-09-18 United Microelectronics Corp. Electrically erasable and programmable read only memory device and manufacturing therefor
US6201737B1 (en) * 2000-01-28 2001-03-13 Advanced Micro Devices, Inc. Apparatus and method to characterize the threshold distribution in an NROM virtual ground array
US6272043B1 (en) * 2000-01-28 2001-08-07 Advanced Micro Devices, Inc. Apparatus and method of direct current sensing from source side in a virtual ground array
US6222768B1 (en) * 2000-01-28 2001-04-24 Advanced Micro Devices, Inc. Auto adjusting window placement scheme for an NROM virtual ground array
TW439276B (en) 2000-02-14 2001-06-07 United Microelectronics Corp Fabricating method of read only memory
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6243300B1 (en) * 2000-02-16 2001-06-05 Advanced Micro Devices, Inc. Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
US6266281B1 (en) * 2000-02-16 2001-07-24 Advanced Micro Devices, Inc. Method of erasing non-volatile memory cells
US6275414B1 (en) * 2000-05-16 2001-08-14 Advanced Micro Devices, Inc. Uniform bitline strapping of a non-volatile memory cell
US6269023B1 (en) * 2000-05-19 2001-07-31 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a current limiter
US6282118B1 (en) * 2000-10-06 2001-08-28 Macronix International Co. Ltd. Nonvolatile semiconductor memory device
JP4151229B2 (ja) * 2000-10-26 2008-09-17 ソニー株式会社 不揮発性半導体記憶装置およびその製造方法
US6602805B2 (en) * 2000-12-14 2003-08-05 Macronix International Co., Ltd. Method for forming gate dielectric layer in NROM
US6487114B2 (en) * 2001-02-28 2002-11-26 Macronix International Co., Ltd. Method of reading two-bit memories of NROM cell
US6461949B1 (en) * 2001-03-29 2002-10-08 Macronix International Co. Ltd. Method for fabricating a nitride read-only-memory (NROM)
TW480677B (en) * 2001-04-04 2002-03-21 Macronix Int Co Ltd Method of fabricating a nitride read only memory cell
TW480678B (en) * 2001-04-13 2002-03-21 Macronix Int Co Ltd Method for producing nitride read only memory (NROM)
JP4776801B2 (ja) * 2001-04-24 2011-09-21 株式会社半導体エネルギー研究所 メモリ回路
US6576511B2 (en) * 2001-05-02 2003-06-10 Macronix International Co., Ltd. Method for forming nitride read only memory
TW494541B (en) * 2001-05-28 2002-07-11 Macronix Int Co Ltd Method for producing silicon nitride read-only-memory
US20020182829A1 (en) 2001-05-31 2002-12-05 Chia-Hsing Chen Method for forming nitride read only memory with indium pocket region
US6531887B2 (en) * 2001-06-01 2003-03-11 Macronix International Co., Ltd. One cell programmable switch using non-volatile cell
US6580135B2 (en) * 2001-06-18 2003-06-17 Macronix International Co., Ltd. Silicon nitride read only memory structure and method of programming and erasure
TW495974B (en) * 2001-06-21 2002-07-21 Macronix Int Co Ltd Manufacturing method for nitride read only memory
US6720614B2 (en) * 2001-08-07 2004-04-13 Macronix International Co., Ltd. Operation method for programming and erasing a data in a P-channel sonos memory cell
US6432778B1 (en) * 2001-08-07 2002-08-13 Macronix International Co. Ltd. Method of forming a system on chip (SOC) with nitride read only memory (NROM)
JP2003163292A (ja) * 2001-08-13 2003-06-06 Halo Lsi Inc ツインｎａｎｄ素子構造、そのアレイ動作およびその製造方法
US6617204B2 (en) * 2001-08-13 2003-09-09 Macronix International Co., Ltd. Method of forming the protective film to prevent nitride read only memory cell charging
JP4734799B2 (ja) * 2001-08-24 2011-07-27 ソニー株式会社 不揮発性半導体メモリ装置の製造方法
TW495977B (en) * 2001-09-28 2002-07-21 Macronix Int Co Ltd Erasing method for p-channel silicon nitride read only memory
TW507369B (en) * 2001-10-29 2002-10-21 Macronix Int Co Ltd Silicon nitride read only memory structure for preventing antenna effect
US6897522B2 (en) * 2001-10-31 2005-05-24 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6514831B1 (en) * 2001-11-14 2003-02-04 Macronix International Co., Ltd. Nitride read only memory cell
US6417053B1 (en) * 2001-11-20 2002-07-09 Macronix International Co., Ltd. Fabrication method for a silicon nitride read-only memory
US6486028B1 (en) * 2001-11-20 2002-11-26 Macronix International Co., Ltd. Method of fabricating a nitride read-only-memory cell vertical structure
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
KR100437466B1 (ko) * 2001-12-27 2004-06-23 삼성전자주식회사 비휘발성 메모리소자 및 그 제조방법
US6421275B1 (en) * 2002-01-22 2002-07-16 Macronix International Co. Ltd. Method for adjusting a reference current of a flash nitride read only memory (NROM) and device thereof
TW521429B (en) * 2002-03-11 2003-02-21 Macronix Int Co Ltd Structure of nitride ROM with protective diode and method for operating the same
US6498377B1 (en) 2002-03-21 2002-12-24 Macronix International, Co., Ltd. SONOS component having high dielectric property
JP2003282744A (ja) 2002-03-22 2003-10-03 Seiko Epson Corp 不揮発性記憶装置
TW529168B (en) * 2002-04-02 2003-04-21 Macronix Int Co Ltd Initialization method of P-type silicon nitride read only memory
JP3983105B2 (ja) * 2002-05-29 2007-09-26 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
TW554489B (en) * 2002-06-20 2003-09-21 Macronix Int Co Ltd Method for fabricating mask ROM device
US20040000689A1 (en) * 2002-06-28 2004-01-01 Erh-Kun Lai Dual-bit MONOS/SONOS memory structure with non-continuous floating gate
US6607957B1 (en) * 2002-07-31 2003-08-19 Macronix International Co., Ltd. Method for fabricating nitride read only memory
US6610586B1 (en) * 2002-09-04 2003-08-26 Macronix International Co., Ltd. Method for fabricating nitride read-only memory
TWI305046B (zh) * 2002-09-09 2009-01-01 Macronix Int Co Ltd
JP2004152924A (ja) * 2002-10-30 2004-05-27 Renesas Technology Corp 半導体記憶素子および半導体装置
US7339822B2 (en) * 2002-12-06 2008-03-04 Sandisk Corporation Current-limited latch
JP2004281662A (ja) * 2003-03-14 2004-10-07 Toshiba Corp 半導体記憶装置及びその製造方法
US6706599B1 (en) * 2003-03-20 2004-03-16 Motorola, Inc. Multi-bit non-volatile memory device and method therefor
KR100525910B1 (ko) * 2003-03-31 2005-11-02 주식회사 하이닉스반도체 플래시 메모리 셀의 프로그램 방법 및 이를 이용한 낸드플래시 메모리의 프로그램 방법
JP4878743B2 (ja) * 2003-10-02 2012-02-15 旺宏電子股▲ふん▼有限公司 Ｎａｎｄ型不揮発性メモリセルの作動方法
US7049651B2 (en) * 2003-11-17 2006-05-23 Infineon Technologies Ag Charge-trapping memory device including high permittivity strips
US7241654B2 (en) * 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330930A (en) * 1980-02-12 1982-05-25 General Instrument Corp. Electrically alterable read only memory semiconductor device made by low pressure chemical vapor deposition process
US5021999A (en) * 1987-12-17 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device with facility of storing tri-level data
US6288943B1 (en) * 2000-07-12 2001-09-11 Taiwan Semiconductor Manufacturing Corporation Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate
US20030062567A1 (en) * 2001-09-28 2003-04-03 Wei Zheng Non volatile dielectric memory cell structure with high dielectric constant capacitive coupling layer
WO2003038907A1 (en) * 2001-10-31 2003-05-08 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
EP1324380A2 (en) * 2001-12-20 2003-07-02 Saifun Semiconductors Ltd Non-volatile memory device and method of fabrication
US20030193062A1 (en) * 2002-04-16 2003-10-16 Fuh-Cheng Jong Nonvolatile memory cell for prevention from second bit effect

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ZENGTAO LIU等.Metal nanocrystal memories-Part II: Electrical Characteristics.IEEE TRANSACTIONS ON ELECTRON DEVICES49 9.2002,49(9),1614-1622.
ZENGTAO LIU等.Metal nanocrystal memories-Part II: Electrical Characteristics.IEEE TRANSACTIONS ON ELECTRON DEVICES49 9.2002,49(9),1614-1622. *

Also Published As

Publication number Publication date
EP1719185A1 (en) 2006-11-08
US20060203555A1 (en) 2006-09-14
US20100039869A1 (en) 2010-02-18
US7911837B2 (en) 2011-03-22
EP2416367A2 (en) 2012-02-08
TW200532925A (en) 2005-10-01
CN1922737A (zh) 2007-02-28
TWI267990B (en) 2006-12-01
JP2011066436A (ja) 2011-03-31
US7616482B2 (en) 2009-11-10
JP4866835B2 (ja) 2012-02-01
KR20060118596A (ko) 2006-11-23
US20050185466A1 (en) 2005-08-25
KR100852849B1 (ko) 2008-08-18
US7072217B2 (en) 2006-07-04
EP2416367A3 (en) 2012-04-04
US7577027B2 (en) 2009-08-18
US20060203554A1 (en) 2006-09-14
WO2005083797A1 (en) 2005-09-09
JP2007523501A (ja) 2007-08-16

Similar Documents

Publication Publication Date Title
CN1922737B (zh) 具有不对称电荷陷获的多态存储器单元
US7609551B2 (en) Semiconductor memory device
US7359241B2 (en) In-service reconfigurable DRAM and flash memory device
US7982256B2 (en) Semiconductor memory device having DRAM cell mode and non-volatile memory cell mode and operation method thereof
US7838920B2 (en) Trench memory structures and operation
JP5059437B2 (ja) 不揮発性半導体記憶装置
US7502262B2 (en) NAND type flash memory array and method for operating the same
JP2005522884A (ja) 半導体メモリ・デバイス
US7728378B2 (en) Nonvolatile semiconductor memory device, manufacturing method thereof and method of programming information into the memory device
CN107093457B (zh) 半导体器件
US6850440B2 (en) Method for improved programming efficiency in flash memory cells
KR20030074191A (ko) 칼럼 기판 코딩을 이용한 고밀도 플래시 메모리 구조
KR100708907B1 (ko) 부스터 라인을 가지는 낸드형 플래시 메모리 소자 및 이의프로그램 방법
JP3891874B2 (ja) 不揮発性メモリ素子
JP2807382B2 (ja) 不揮発性記憶装置およびその情報の書き込み方法
JP2002064158A (ja) 不揮発性半導体記憶装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant